[PATCH] D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas updated this revision to Diff 477532.
cdevadas added a comment.

Rebase + Incorporated changes after D138515 <https://reviews.llvm.org/D138515> to move the handling of physReg to current VirtReg mapping entirely into the generic design.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124196/new/

https://reviews.llvm.org/D124196

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/SIDefines.h
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
  llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
  llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
  llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
  llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
  llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
  llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
  llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
  llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
  llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
  llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
  llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
  llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
  llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
  llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
  llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
  llvm/test/CodeGen/AMDGPU/spill192.mir
  llvm/test/CodeGen/AMDGPU/spill224.mir
  llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
  llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
  llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
  llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
  llvm/test/CodeGen/AMDGPU/wwm-register-spill-during-regalloc.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
  llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
  llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
  llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
  llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir