[PATCH] D138424: [TargetLowering][AArch64] Teach DemandedBits about SVE count intrinsics

[Benjamin Maxwell via Phabricator via llvm-commits]

benmxwl-arm updated this revision to Diff 477507.
benmxwl-arm added a comment.

Simplified to use `Subtarget->getMaxSVEVectorSizeInBits()` (which is already based off the `vscale_range()` attribute).

This now depends on https://reviews.llvm.org/D138575 (currently `getMaxSVEVectorSizeInBits()` only checks for `hasSVE()`,
which means it breaks for SME). Until that lands there will be a few test breakages.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138424/new/

https://reviews.llvm.org/D138424

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

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