[PATCH] D138570: [AArch64] Add patterns for SVE predicated add/sub and mov combine

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I agree this sounds nicer than the sext patch - that one looked like there was much more involved than we were hoping for.



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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3137
+let Predicates = [HasSVE] in {
+    multiclass sve_predicated_add<SDNode extend, int value> {
+      def : Pat<(nxv16i8 (add ZPR:$op, (extend (nxv16i1 PPR:$pred)))),
----------------
The indenting can be a little lower here.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3152
+    def : Pat<(nxv16i8 (sub ZPR:$op, (sext (nxv16i1 PPR:$pred)))),
+            (SUB_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B -1, 0))>;
+    def : Pat<(nxv8i16 (sub ZPR:$op, (sext (nxv8i1 PPR:$pred)))),
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I think these constants should be in the range 0-255. Only the bottom 8 bits are likely used, so -1 will mean the same thing, but it's best if we can generate instructions more precisely if we can.

Something like this link can be used to check the constants we need for different values: https://godbolt.org/z/9K7ozhYo7


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138570/new/

https://reviews.llvm.org/D138570