[PATCH] D138424: [TargetLowering][AArch64] Teach DemandedBits about SVE count intrinsics

Wed Nov 23 04:56:40 PST 2022

benmxwl-arm updated this revision to Diff 477466.
benmxwl-arm retitled this revision from " [TargetLowering][AArch64] Teach DemandedBits about SVE count intrinsics" to "[TargetLowering][AArch64] Teach DemandedBits about SVE count intrinsics".
benmxwl-arm edited the summary of this revision.
benmxwl-arm added a comment.

- Moved CNTx intrinsic check into switch
- Now base the MaxElements off VScaleRange if present, otherwise fallback to SVEMaxBitsPerVector
- Switched to Log2_32

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138424/new/

https://reviews.llvm.org/D138424

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

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