[PATCH] D138492: [AMDGPU][AsmParser] Refine parsing instruction operands.
Ivan Kosarev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 23 02:24:53 PST 2022
kosarev added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:379
+ bool isTFE() const {
+ return isImmTy(ImmTyTFE) || (isToken() && getToken() == "tfe");
+ }
----------------
foad wrote:
> Why does only tfe need this?
An earlier version of the patch used to parse `tfe` operands into both `ImmTyTFE`s and tokens, later changed to use `ImmTyTFE` in all cases for simplicity. I've removed this check and changed the rest of the code to employ `parseNamedBit()` for parsing hardcoded `tfe`s. Same is done for `gds`, another operand we use in both the hardcoded and `AsmOperand` forms.
There's a similar situation with `off`, parsed into tokens while also having `parseVReg32OrOff()` adding them as `ImmTyOff`s. I'd prefer to address this separately along with other things like `ImmTyIdxen` being effectively unused, etc.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138492/new/
https://reviews.llvm.org/D138492
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