[PATCH] D138551: [PowerPC] Mask constant operands in bit permutation calculation

[Qiu Chaofan via Phabricator via llvm-commits]

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This patch fixes issue 59074 <https://github.com/llvm/llvm-project/issues/59074>.

In IR or C code, left/right shift amount larger than value size is undefined behavior. But in practise, backend lowering for `srl_parts/sra_parts/shl_parts` produces add/sub of shift amounts, thus constant shift amounts might be negative or larger than value size. And the lowering depends on behavior in ISA.

PowerPC ISA says, the lowest 7 bits (6 bits if in 32-bit instruction) will be taken, and if the highest among them is 1, result will be zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift amount.

This patch emulates the behavior and avoids array overflow in bit permutation's value bits calculator.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138551

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/test/CodeGen/PowerPC/pr59074.ll

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