[llvm] 4bb6e22 - [Hexagon] Add missing patterns for select

[Krzysztof Parzyszek via llvm-commits]

Author: Ikhlas Ajbar
Date: 2022-11-22T12:20:38-08:00
New Revision: 4bb6e220a002ab23e835a28364fdf071ef87d0d5

URL: https://github.com/llvm/llvm-project/commit/4bb6e220a002ab23e835a28364fdf071ef87d0d5
DIFF: https://github.com/llvm/llvm-project/commit/4bb6e220a002ab23e835a28364fdf071ef87d0d5.diff

LOG: [Hexagon] Add missing patterns for select

Fixes https://github.com/llvm/llvm-project/issues/59077.

Added: 
    llvm/test/CodeGen/Hexagon/isel/select-vec.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index ac4a352548bf9..a75ac0e1378ef 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -875,6 +875,10 @@ def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto,   i1, F64>;
 
 def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt),
          (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>;
+def: Pat<(select I1:$Pu, v4i8:$Rs, v4i8:$Rt),
+         (C2_mux I1:$Pu, v4i8:$Rs, v4i8:$Rt)>;
+def: Pat<(select I1:$Pu, v2i16:$Rs, v2i16:$Rt),
+         (C2_mux I1:$Pu, v2i16:$Rs, v2i16:$Rt)>;
 def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs),
          (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
 def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8),
@@ -897,6 +901,10 @@ def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt),
          (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
                    (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
 
+def: Pat<(select I1:$Pu, v2i32:$Rs, v2i32:$Rt),
+         (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
+                   (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
+
 def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I),
          (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>;
 def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt),

diff  --git a/llvm/test/CodeGen/Hexagon/isel/select-vec.ll b/llvm/test/CodeGen/Hexagon/isel/select-vec.ll
new file mode 100644
index 0000000000000..4e54aa4212247
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/select-vec.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1, i32 %a2) #0 {
+; CHECK-LABEL: f0:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = cmp.eq(r2,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,r0,r1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = icmp eq i32 %a2, 0
+  %v1 = select i1 %v0, <4 x i8> %a0, <4 x i8> %a1
+  ret <4 x i8> %v1
+}
+
+define <8 x i8> @f1(<8 x i8> %a0, <8 x i8> %a1, i32 %a2) #0 {
+; CHECK-LABEL: f1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = cmp.eq(r4,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,r0,r2)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     r1 = mux(p0,r1,r3)
+; CHECK-NEXT:    }
+  %v0 = icmp eq i32 %a2, 0
+  %v1 = select i1 %v0, <8 x i8> %a0, <8 x i8> %a1
+  ret <8 x i8> %v1
+}
+
+define <2 x i16> @f2(<2 x i16> %a0, <2 x i16> %a1, i32 %a2) #0 {
+; CHECK-LABEL: f2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = cmp.eq(r2,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,r0,r1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = icmp eq i32 %a2, 0
+  %v1 = select i1 %v0, <2 x i16> %a0, <2 x i16> %a1
+  ret <2 x i16> %v1
+}
+
+define <4 x i16> @f3(<4 x i16> %a0, <4 x i16> %a1, i32 %a2) #0 {
+; CHECK-LABEL: f3:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = cmp.eq(r4,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,r0,r2)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     r1 = mux(p0,r1,r3)
+; CHECK-NEXT:    }
+  %v0 = icmp eq i32 %a2, 0
+  %v1 = select i1 %v0, <4 x i16> %a0, <4 x i16> %a1
+  ret <4 x i16> %v1
+}
+
+define <2 x i32> @f4(<2 x i32> %a0, <2 x i32> %a1, i32 %a2) #0 {
+; CHECK-LABEL: f4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = cmp.eq(r4,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,r0,r2)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     r1 = mux(p0,r1,r3)
+; CHECK-NEXT:    }
+  %v0 = icmp eq i32 %a2, 0
+  %v1 = select i1 %v0, <2 x i32> %a0, <2 x i32> %a1
+  ret <2 x i32> %v1
+}
+
+attributes #0 = { nounwind }