[PATCH] D138493: [AMDGPU][NFC] Remove isLegalVOP3PShuffleMask
Pierre van Houtryve via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 22 06:32:07 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4d39552abea3: [AMDGPU][NFC] Remove isLegalVOP3PShuffleMask (authored by Pierre-vh).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138493/new/
https://reviews.llvm.org/D138493
Files:
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
Index: llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
+++ llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
@@ -27,7 +27,6 @@
getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
GISelKnownBits *KnownBits = nullptr);
-bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask);
bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty);
}
}
Index: llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -64,15 +64,6 @@
return std::make_pair(Reg, 0);
}
-bool AMDGPU::isLegalVOP3PShuffleMask(ArrayRef<int> Mask) {
- assert(Mask.size() == 2);
-
- // If one half is undef, the other is trivially in the same reg.
- if (Mask[0] == -1 || Mask[1] == -1)
- return true;
- return (Mask[0] & 2) == (Mask[1] & 2);
-}
-
bool AMDGPU::hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget,
const LLT &Ty) {
if (Ty == LLT::scalar(32))
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