[PATCH] D138492: [AMDGPU][AsmParser] Refine parsing instruction operands.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added a comment.

For operands that we know should never be considered valid expressions (such as `id:...` ones maybe?), this can be improved further by parsing them regardless of the instruction they are used in and their position. Also, for register operands we could call `parseReg()` directly from `parseCustomOperand()` instead of falling back to that after considering other possibilities in `parseOperand()`.



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Comment at: llvm/utils/TableGen/AsmMatcherEmitter.cpp:1463-1469
+      if (CallCustomParserForAllOperands || !Op.Class->ParserMethod.empty()) {
+        unsigned &OperandMask = OpClassMask[Op.Class];
+        OperandMask |= maskTrailingOnes<unsigned>(NumOptionalOps + 1)
+                       << (i - NumOptionalOps);
+      }
+      if (Op.Class->IsOptional)
+        ++NumOptionalOps;
----------------
Apart from allowing calling custom parsers for all operands, this also fixes marking possible positions of operands that come after optional operands.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138492/new/

https://reviews.llvm.org/D138492