[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

[Ties Stuij via Phabricator via llvm-commits]

stuij marked an inline comment as done.
stuij added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:11725
+    : BaseTwoOperandRegReg<size, 0b0, {0,1,1,0,?,?}, regtype, asm, OpNode>,
+      Sched<[]> {
+  let Inst{11} = isMin;
----------------
dmgreen wrote:
> stuij wrote:
> > dmgreen wrote:
> > > Can we make this WriteI, maybe. I think that would probably be the closest sched class.
> > I'm assuming you meant WriteLD.
> That would be a Load I believe. There are the min/max instructions?  I think "simple ALU instruction" should be the closest match, which would be WriteI
ah right, sorry misread your comment.


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https://reviews.llvm.org/D138488