[llvm] 219417b - [RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension
via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 22 01:22:31 PST 2022
Author: WuXinlong
Date: 2022-11-22T17:22:26+08:00
New Revision: 219417b2c638e22e3baaad53680a811cc9db4dff
URL: https://github.com/llvm/llvm-project/commit/219417b2c638e22e3baaad53680a811cc9db4dff
DIFF: https://github.com/llvm/llvm-project/commit/219417b2c638e22e3baaad53680a811cc9db4dff.diff
LOG: [RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension
This patch add the support of RISCV Zca ext
`Zca` is a subset of C extension instructions that are compatible with the Zc extension.
So this patch implements Zca code generation with reference to the C extension and sets the 2-byte alignment for the Zca extension, just like C extension does.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D130483
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/align.s
llvm/test/MC/RISCV/rv32c-aliases-valid.s
llvm/test/MC/RISCV/rv64c-aliases-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 86c8af874d2da..b7bc416c83116 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2098,6 +2098,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
"unexpected token, expected end of statement");
clearFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureExtZca, "+experimental-zca");
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index a1d7cf1ef8b79..9f23cafdd7264 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -365,10 +365,11 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
Count -= 1;
}
+ bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
+ bool HasStdExtZca = STI->getFeatureBits()[RISCV::FeatureExtZca];
// The canonical nop on RVC is c.nop.
if (Count % 4 == 2) {
- OS.write(STI->getFeatureBits()[RISCV::FeatureStdExtC] ? "\x01\0" : "\0\0",
- 2);
+ OS.write((HasStdExtC || HasStdExtZca) ? "\x01\0" : "\0\0", 2);
Count -= 2;
}
@@ -595,8 +596,9 @@ bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
if (!STI->getFeatureBits()[RISCV::FeatureRelax])
return false;
- bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
- unsigned MinNopLen = HasStdExtC ? 2 : 4;
+ bool UseCompressedNop = STI->getFeatureBits()[RISCV::FeatureStdExtC] ||
+ STI->getFeatureBits()[RISCV::FeatureExtZca];
+ unsigned MinNopLen = UseCompressedNop ? 2 : 4;
if (AF.getAlignment() <= MinNopLen) {
return false;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
index 554711e875211..ef2ec87338d73 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp
@@ -19,5 +19,8 @@ using namespace llvm;
unsigned RISCVMCObjectFileInfo::getTextSectionAlignment() const {
const MCSubtargetInfo *STI = getContext().getSubtargetInfo();
- return STI->hasFeature(RISCV::FeatureStdExtC) ? 2 : 4;
+ return (STI->hasFeature(RISCV::FeatureStdExtC) ||
+ STI->hasFeature(RISCV::FeatureExtZca))
+ ? 2
+ : 4;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9f47fb2730b7f..d4d055b0da074 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -977,7 +977,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
// Function alignments.
- const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
+ const Align FunctionAlignment(Subtarget.hasStdExtCOrZca() ? 2 : 4);
setMinFunctionAlignment(FunctionAlignment);
setPrefFunctionAlignment(FunctionAlignment);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a560c87f3ab25..c1090e6e164a4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -58,7 +58,7 @@ RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
STI(STI) {}
MCInst RISCVInstrInfo::getNop() const {
- if (STI.getFeatureBits()[RISCV::FeatureStdExtC])
+ if (STI.hasStdExtCOrZca())
return MCInstBuilder(RISCV::C_NOP);
return MCInstBuilder(RISCV::ADDI)
.addReg(RISCV::X0)
@@ -1707,8 +1707,10 @@ outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
// jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
unsigned FrameOverhead = 4;
- if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
- .getFeatureBits()[RISCV::FeatureStdExtC])
+ if (RepeatedSequenceLocs[0]
+ .getMF()
+ ->getSubtarget<RISCVSubtarget>()
+ .hasStdExtCOrZca())
FrameOverhead = 2;
return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 7cef6b4e20203..be44a021b987c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -756,69 +756,69 @@ def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SP:$rs1, 0)>;
// on page 82 of the ISA manual.
// Quadrant 0
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
(C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtD] in {
def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
(C_FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtD]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
(C_LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
def : CompressPat<(FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
(C_FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def : CompressPat<(LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
(C_LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, IsRV64]
+} // Predicates = [HasStdExtCOrZca, IsRV64]
let Predicates = [HasStdExtC, HasStdExtD] in {
def : CompressPat<(FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
(C_FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtD]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm),
(C_SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
def : CompressPat<(FSW FPR32C:$rs2, GPRC:$rs1, uimm7_lsb00:$imm),
(C_FSW FPR32C:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def : CompressPat<(SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
(C_SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, IsRV64]
+} // Predicates = [HasStdExtCOrZca, IsRV64]
// Quadrant 1
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
(C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
-let Predicates = [HasStdExtC, IsRV32] in {
+let Predicates = [HasStdExtCOrZca, IsRV32] in {
def : CompressPat<(JAL X1, simm12_lsb0:$offset),
(C_JAL simm12_lsb0:$offset)>;
-} // Predicates = [HasStdExtC, IsRV32]
+} // Predicates = [HasStdExtCOrZca, IsRV32]
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def : CompressPat<(ADDIW GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm),
(C_ADDIW GPRNoX0:$rs1, simm6:$imm)>;
-} // Predicates = [HasStdExtC, IsRV64]
+} // Predicates = [HasStdExtCOrZca, IsRV64]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
(C_LI GPRNoX0:$rd, simm6:$imm)>;
def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
@@ -848,9 +848,9 @@ def : CompressPat<(AND GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
let isCompressOnly = true in
def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
(C_AND GPRC:$rs1, GPRC:$rs2)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
let isCompressOnly = true in
def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm),
(C_LI GPRNoX0:$rd, simm6:$imm)>;
@@ -861,44 +861,44 @@ def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
let isCompressOnly = true in
def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
(C_ADDW GPRC:$rs1, GPRC:$rs2)>;
-} // Predicates = [HasStdExtC, IsRV64]
+} // Predicates = [HasStdExtCOrZca, IsRV64]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(JAL X0, simm12_lsb0:$offset),
(C_J simm12_lsb0:$offset)>;
def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
// Quadrant 2
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
(C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtD] in {
def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
(C_FLDSP FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtD]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(LW GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm),
(C_LWSP GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
def : CompressPat<(FLW FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm),
(C_FLWSP FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def : CompressPat<(LD GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm),
(C_LDSP GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, IsRV64]
+} // Predicates = [HasStdExtCOrZca, IsRV64]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
(C_JR GPRNoX0:$rs1)>;
let isCompressOnly = true in {
@@ -918,24 +918,24 @@ def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
let isCompressOnly = true in
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtD] in {
def : CompressPat<(FSD FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm),
(C_FSDSP FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtD]
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(SW GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm),
(C_SWSP GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
def : CompressPat<(FSW FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm),
(C_FSWSP FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def : CompressPat<(SD GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm),
(C_SDSP GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, IsRV64]
+} // Predicates = [HasStdExtCOrZca, IsRV64]
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 418c878d10af4..fa7c5c064ded4 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -158,6 +158,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtF() const { return HasStdExtF; }
bool hasStdExtD() const { return HasStdExtD; }
bool hasStdExtC() const { return HasStdExtC; }
+ bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
bool hasStdExtV() const { return HasStdExtV; }
bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 867d12b00b473..8301076952f14 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -38,6 +38,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
+
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -79,6 +81,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefix=RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -118,6 +121,7 @@
; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
+; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -160,6 +164,7 @@
; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
+; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s
index cd9f47a7dd4b5..72cf37581d10d 100644
--- a/llvm/test/MC/RISCV/align.s
+++ b/llvm/test/MC/RISCV/align.s
@@ -17,16 +17,30 @@
# Relaxation enabled with C extension:
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
# RUN: | llvm-objdump -d -M no-aliases - \
-# RUN: | FileCheck -check-prefix=C-EXT-RELAX-INST %s
+# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
-# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-EXT-RELAX-RELOC %s
+# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-RELOC %s
+
+# Relaxation enabled with Zca extension:
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,+relax < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -d -M no-aliases - \
+# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,+relax < %s \
+# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-RELAX-RELOC %s
# Relaxation disabled with C extension:
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \
# RUN: | llvm-objdump -d -M no-aliases - \
-# RUN: | FileCheck -check-prefix=C-EXT-NORELAX-INST %s
+# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \
-# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-EXT-NORELAX-RELOC %s
+# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-RELOC %s
+
+# Relaxation disabled with ZCA extension:
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,-relax < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -d -M no-aliases - \
+# RUN: | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca,-relax < %s \
+# RUN: | llvm-readobj -r - | FileCheck -check-prefix=C-OR-ZCA-EXT-NORELAX-RELOC %s
# We need to insert N-MinNopSize bytes NOPs and R_RISCV_ALIGN relocation
# type for .align N directive when linker relaxation enabled.
@@ -34,23 +48,23 @@
# The first R_RISCV_ALIGN come from
# MCELFStreamer::InitSections() emitCodeAlignment(getTextSectionAligntment()).
-# C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2
-# C-EXT-RELAX-INST: c.nop
+# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2
+# C-OR-ZCA-EXT-RELAX-INST: c.nop
test:
.p2align 2
# If the +c extension is enabled, the text section will be 2-byte aligned, so
# one c.nop instruction is sufficient.
-# C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0x2
-# C-EXT-RELAX-INST-NOT: c.nop
+# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0x2
+# C-OR-ZCA-EXT-RELAX-INST-NOT: c.nop
bne zero, a0, .LBB0_2
mv a0, zero
.p2align 3
# RELAX-RELOC: R_RISCV_ALIGN - 0x4
# RELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
-# C-EXT-RELAX-INST: c.nop
-# C-EXT-RELAX-INST: addi zero, zero, 0
-# C-EXT-NORELAX-INST: addi zero, zero, 0
+# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
+# C-OR-ZCA-EXT-RELAX-INST: c.nop
+# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
+# C-OR-ZCA-EXT-NORELAX-INST: addi zero, zero, 0
add a0, a0, a1
.align 4
.LBB0_2:
@@ -59,11 +73,11 @@ test:
# RELAX-INST: addi zero, zero, 0
# RELAX-INST: addi zero, zero, 0
# NORELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0xE
-# C-EXT-RELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-INST: c.nop
+# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0xE
+# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
+# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
+# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
+# C-OR-ZCA-EXT-RELAX-INST: c.nop
# C-EXT-INST: addi zero, zero, 0
# C-EXT-INST: c.nop
add a0, a0, a1
@@ -73,9 +87,9 @@ test:
# RELAX-RELOC: R_RISCV_ALIGN - 0x4
# RELAX-INST: addi zero, zero, 0
# NORELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
-# C-EXT-RELAX-INST: addi zero, zero, 0
-# C-EXT-RELAX-INST-NOT: c.nop
+# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
+# C-OR-ZCA-EXT-RELAX-INST: addi zero, zero, 0
+# C-OR-ZCA-EXT-RELAX-INST-NOT: c.nop
# C-EXT-INST: addi zero, zero, 0
# C-EXT-INST: c.nop
add a0, a0, a1
@@ -86,12 +100,12 @@ test:
# RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xC
# RELAX-INST: 01 01
# RELAX-INST: 01 01
-# C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xE
-# C-EXT-RELAX-INST: 01 01
+# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xE
+# C-OR-ZCA-EXT-RELAX-INST: 01 01
# C-EXT-INST: 01 01
ret
# NORELAX-RELOC-NOT: R_RISCV
-# C-EXT-NORELAX-RELOC-NOT: R_RISCV
+# C-OR-ZCA-EXT-NORELAX-RELOC-NOT: R_RISCV
# Code alignment of a byte size less than the size of a nop must be treated
# as no alignment. This used to trigger a fatal error with relaxation enabled
# as the calculation to emit the worst-case sequence of nops would overflow.
@@ -104,18 +118,18 @@ test:
.data
.p2align 3
# RELAX-RELOC-NOT: R_RISCV_ALIGN
-# C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
+# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
data1:
.word 7
.p2align 4
# RELAX-RELOC-NOT: R_RISCV_ALIGN
-# C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
+# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN
data2:
.word 9
# Check that the initial alignment is properly handled when using .option to
# disable the C extension. This used to crash.
-# C-EXT-RELAX-INST: <.text2>:
-# C-EXT-RELAX-INST-NEXT: add a0, a0, a1
+# C-OR-ZCA-EXT-RELAX-INST: <.text2>:
+# C-OR-ZCA-EXT-RELAX-INST-NEXT: add a0, a0, a1
.section .text2, "x"
.option norvc
.balign 4
diff --git a/llvm/test/MC/RISCV/rv32c-aliases-valid.s b/llvm/test/MC/RISCV/rv32c-aliases-valid.s
index f2a03e7664ef0..a0a1e8199ab0f 100644
--- a/llvm/test/MC/RISCV/rv32c-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-aliases-valid.s
@@ -3,6 +3,11 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
# RUN: | llvm-objdump -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+experimental-zca -riscv-no-aliases < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zca < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
# The following check prefixes are used in this test:
# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
diff --git a/llvm/test/MC/RISCV/rv64c-aliases-valid.s b/llvm/test/MC/RISCV/rv64c-aliases-valid.s
index db6ea5ec5ac04..5b5dacee9b81d 100644
--- a/llvm/test/MC/RISCV/rv64c-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-aliases-valid.s
@@ -3,6 +3,11 @@
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
# RUN: | llvm-objdump -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+experimental-zca -riscv-no-aliases < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zca < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
# The following check prefixes are used in this test:
# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
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