[PATCH] D136051: [CodeGen] Introduce a flag to allow same cycle def-use schedule

[Suyog Sarda via Phabricator via llvm-commits]

ssarda added a comment.

In D136051#3931086 <https://reviews.llvm.org/D136051#3931086>, @bcahoon wrote:

> Hi @ssarda, thanks for the test case. That helps to understand the problem. Which appears to be the following MIR,
>
>   INLINEASM &"$0 = insert($1,#31,#1);" [attdialect], $0:[regdef], implicit-def $r7, $1:[reguse:IntRegs], %45:intregs
>   %32:intregs = COPY $r7
>   $r7 = COPY %32:intregs
>
> These instructions are scheduled in the same cycle. Then, isValidSchedule rejects this because :
>
>   // Furthermore, if a physical def/use pair is assigned to the same
>   // cycle, orderDependence does not guarantee def/use ordering, so that
>   // case should be considered invalid.

You are right @bcahoon.

> That means that orderDependence could reorder those instructions after pipelining?

For Hexagon, i haven't come across a case yet where the orderDependence is re-ordering instructions in such a way that use is scheduled before def. 
Moreover, if there is a problem in orderDependence not guaranteeing def scheduled before use, then the fix should go in orderDependence() function.
I feel that by putting stricter checks in isValidSchedule() function for same cycle, we are penalizing pipeliner resulting in un-pipelined code.


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