[llvm] b39b76f - [X86] Allow no X87 on 32-bit
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 21 18:47:53 PST 2022
Author: Phoebe Wang
Date: 2022-11-22T10:47:47+08:00
New Revision: b39b76f2ef30c75734baa04fc236fff621b65833
URL: https://github.com/llvm/llvm-project/commit/b39b76f2ef30c75734baa04fc236fff621b65833
DIFF: https://github.com/llvm/llvm-project/commit/b39b76f2ef30c75734baa04fc236fff621b65833.diff
LOG: [X86] Allow no X87 on 32-bit
This patch is an alternative of D100091. It solved the problems in `f80` type lowering.
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D137946
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrFormats.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index b61703c46457..22876ef7da6d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -999,7 +999,7 @@ class TargetLoweringBase {
/// register, this contains one step in the expansion to get to the smaller
/// register. For illegal floating point types, this returns the integer type
/// to transform to.
- EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
+ virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
return getTypeConversion(Context, VT).second;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index 8fe9a83b9c3d..6fdd3fb7e0dc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -722,9 +722,13 @@ void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
}
void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
- assert(Result.getValueType() ==
- TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
+#ifndef NDEBUG
+ EVT VT = Result.getValueType();
+ LLVMContext &Ctx = *DAG.getContext();
+ assert((VT == EVT::getIntegerVT(Ctx, 80) ||
+ VT == TLI.getTypeToTransformTo(Ctx, Op.getValueType())) &&
"Invalid type for softened float");
+#endif
AnalyzeNewValue(Result);
auto &OpIdEntry = SoftenedFloats[getTableId(Op)];
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 03325b204410..18c7b38c1d5e 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1349,6 +1349,15 @@ void TargetLoweringBase::computeRegisterProperties(
ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
}
+ // Decide how to handle f80. If the target does not have native f80 support,
+ // expand it to i96 and we will be generating soft float library calls.
+ if (!isTypeLegal(MVT::f80)) {
+ NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
+ RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
+ TransformToType[MVT::f80] = MVT::i32;
+ ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);
+ }
+
// Decide how to handle f64. If the target does not have native f64 support,
// expand it to i64 and we will be generating soft float library calls.
if (!isTypeLegal(MVT::f64)) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e9d41405643c..2e64c20e112c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -21322,7 +21322,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Ext);
}
- if (VT == MVT::f128)
+ if (VT == MVT::f128 || !Subtarget.hasX87())
return SDValue();
SDValue ValueToStore = Src;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index c539ba32d147..2776fa00243d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1514,6 +1514,12 @@ namespace llvm {
Align getPrefLoopAlignment(MachineLoop *ML) const override;
+ EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const override {
+ if (VT == MVT::f80)
+ return EVT::getIntegerVT(Context, 96);
+ return TargetLoweringBase::getTypeToTransformTo(Context, VT);
+ }
+
protected:
std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI,
diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index ba0ba8e63328..165dbb85c8e7 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -473,13 +473,15 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
: I<o, F, outs, ins, asm, []> {
let Defs = [FPSW];
+ let Predicates = [HasX87];
}
-// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
+// FpI_ - Floating Point Pseudo Instruction template.
class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
: PseudoI<outs, ins, pattern> {
let FPForm = fp;
let Defs = [FPSW];
+ let Predicates = [HasX87];
}
// Templates for instructions that use a 16- or 32-bit segmented address as
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 93405cab6e34..2ed7e4577e88 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -931,6 +931,7 @@ def HasAES : Predicate<"Subtarget->hasAES()">;
def HasVAES : Predicate<"Subtarget->hasVAES()">;
def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">;
def HasFXSR : Predicate<"Subtarget->hasFXSR()">;
+def HasX87 : Predicate<"Subtarget->hasX87()">;
def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">;
def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">;
def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">;
diff --git a/llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll b/llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll
index e1ccede445d8..19554e652e4c 100644
--- a/llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll
+++ b/llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll
@@ -117,7 +117,6 @@ entry:
ret double %0
}
-; FIXME: We should not generate x87 instructions when x87 is disabled.
define x86_fp80 @f6(x86_fp80 %a, x86_fp80 %b) nounwind {
; X87-LABEL: f6:
; X87: # %bb.0: # %entry
@@ -128,31 +127,17 @@ define x86_fp80 @f6(x86_fp80 %a, x86_fp80 %b) nounwind {
;
; NOX87-LABEL: f6:
; NOX87: # %bb.0: # %entry
-; NOX87-NEXT: pushl %ebp
-; NOX87-NEXT: movl %esp, %ebp
-; NOX87-NEXT: andl $-8, %esp
-; NOX87-NEXT: subl $48, %esp
-; NOX87-NEXT: movl 20(%ebp), %eax
-; NOX87-NEXT: movl 24(%ebp), %ecx
-; NOX87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; NOX87-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; NOX87-NEXT: movl 28(%ebp), %eax
-; NOX87-NEXT: movw %ax, {{[0-9]+}}(%esp)
-; NOX87-NEXT: movl 8(%ebp), %eax
-; NOX87-NEXT: movl 12(%ebp), %ecx
-; NOX87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; NOX87-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; NOX87-NEXT: movl 16(%ebp), %eax
-; NOX87-NEXT: movw %ax, {{[0-9]+}}(%esp)
-; NOX87-NEXT: fldt {{[0-9]+}}(%esp)
-; NOX87-NEXT: fldt {{[0-9]+}}(%esp)
-; NOX87-NEXT: faddp %st, %st(1)
-; NOX87-NEXT: fstpt (%esp)
-; NOX87-NEXT: movl (%esp), %eax
-; NOX87-NEXT: movl {{[0-9]+}}(%esp), %edx
+; NOX87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; NOX87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
-; NOX87-NEXT: movl %ebp, %esp
-; NOX87-NEXT: popl %ebp
+; NOX87-NEXT: pushl %ecx
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: pushl %eax
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: calll __addxf3
+; NOX87-NEXT: addl $24, %esp
+; NOX87-NEXT: movzwl %cx, %ecx
; NOX87-NEXT: retl
entry:
%0 = fadd x86_fp80 %a, %b
@@ -191,3 +176,52 @@ entry:
%2 = insertvalue {float, float, float} %1, float %b, 2
ret {float, float, float} %2
}
+
+define x86_fp80 @f8(i64 %a) nounwind {
+; X87-LABEL: f8:
+; X87: # %bb.0: # %entry
+; X87-NEXT: fildll {{[0-9]+}}(%esp)
+; X87-NEXT: retl
+;
+; NOX87-LABEL: f8:
+; NOX87: # %bb.0: # %entry
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: calll __floatdixf
+; NOX87-NEXT: addl $8, %esp
+; NOX87-NEXT: movzwl %cx, %ecx
+; NOX87-NEXT: retl
+entry:
+ %0 = sitofp i64 %a to x86_fp80
+ ret x86_fp80 %0
+}
+
+define i32 @f9(x86_fp80 %a) nounwind {
+; X87-LABEL: f9:
+; X87: # %bb.0: # %entry
+; X87-NEXT: subl $8, %esp
+; X87-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-NEXT: fnstcw (%esp)
+; X87-NEXT: movzwl (%esp), %eax
+; X87-NEXT: orl $3072, %eax # imm = 0xC00
+; X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
+; X87-NEXT: fldcw {{[0-9]+}}(%esp)
+; X87-NEXT: fistpl {{[0-9]+}}(%esp)
+; X87-NEXT: fldcw (%esp)
+; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X87-NEXT: addl $8, %esp
+; X87-NEXT: retl
+;
+; NOX87-LABEL: f9:
+; NOX87: # %bb.0: # %entry
+; NOX87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; NOX87-NEXT: pushl %eax
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT: calll __fixxfsi
+; NOX87-NEXT: addl $12, %esp
+; NOX87-NEXT: retl
+entry:
+ %0 = fptosi x86_fp80 %a to i32
+ ret i32 %0
+}
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