[PATCH] D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat)
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 21 18:31:38 PST 2022
pcwang-thead marked an inline comment as done.
pcwang-thead added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll:273
; NOT-OPTIMIZED-NEXT: vle8.v v8, (a6)
-; NOT-OPTIMIZED-NEXT: vadd.vx v8, v8, a5
+; NOT-OPTIMIZED-NEXT: vmv.v.x v9, a5
+; NOT-OPTIMIZED-NEXT: vdivu.vv v8, v9, v8
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reames wrote:
> This looks like a regression.
The diff result seems weird, but I think it's what we expected.
I added a new test `gather_zero_stride_unfold` (copied from `gather_zero_stride`) in which I changed `%4 = add <32 x i8> %wide.load, %wide.masked.gather` to `%4 = udiv <32 x i8> %wide.masked.gather, %wide.load` so that splat can't be folded since division is not commutative. So here are scalar load(`lbu a5, 0(a1)`) and vector splat(`vmv.v.x v9, a5`).
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https://reviews.llvm.org/D138101/new/
https://reviews.llvm.org/D138101
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