[llvm] 2b1e895 - [PowerPC] Add support for G_ADD and G_SUB.

[Kai Nacke via llvm-commits]

Author: Kai Nacke
Date: 2022-11-21T23:35:17Z
New Revision: 2b1e895afb5b79b076db07d51b6118183356e68d

URL: https://github.com/llvm/llvm-project/commit/2b1e895afb5b79b076db07d51b6118183356e68d
DIFF: https://github.com/llvm/llvm-project/commit/2b1e895afb5b79b076db07d51b6118183356e68d.diff

LOG: [PowerPC] Add support for G_ADD and G_SUB.

Extends the global isel implementation to support G_ADD and G_SUB.

Reviewed By: arsenm, amyk

Differential Revision: https://reviews.llvm.org/D128106

Added: 
    llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll

Modified: 
    llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
    llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
index be56b6fe49589..bbbd211269d42 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -27,5 +27,8 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_ADD, G_SUB})
+      .legalFor({S64})
+      .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index 2eb9ec2c2b085..8a57010299d65 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -60,6 +60,9 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   unsigned MappingID = DefaultMappingID;
 
   switch (Opc) {
+    // Arithmetic ops.
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:

diff  --git a/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
new file mode 100644
index 0000000000000..5275436d1bc5a
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple ppc64le-linux -ppc-asm-full-reg-names -global-isel -o - < %s \
+; RUN:     | FileCheck %s
+
+define i8 @test_addi8(i8 %a, i8 %b) {
+; CHECK-LABEL: test_addi8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i8 %a, %b
+  ret i8 %res
+}
+
+define i16 @test_addi16(i16 %a, i16 %b) {
+; CHECK-LABEL: test_addi16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i16 %a, %b
+  ret i16 %res
+}
+
+define i32 @test_addi32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_addi32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i32 %a, %b
+  ret i32 %res
+}
+
+define i64 @test_addi64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_addi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = add i64 %a, %b
+  ret i64 %res
+}
+
+define i8 @test_subi8(i8 %a, i8 %b) {
+; CHECK-LABEL: test_subi8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i8 %a, %b
+  ret i8 %res
+}
+
+define i16 @test_subi16(i16 %a, i16 %b) {
+; CHECK-LABEL: test_subi16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i16 %a, %b
+  ret i16 %res
+}
+
+define i32 @test_subi32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_subi32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i32 %a, %b
+  ret i32 %res
+}
+
+define i64 @test_subi64(i64 %a, i64 %b) {
+; CHECK-LABEL: test_subi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    blr
+  %res = sub i64 %a, %b
+  ret i64 %res
+}