[llvm] bd68070 - [PowerPC] Add new load/store with length instructions to Future CPU.
Maryam Moghadas via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 21 11:22:31 PST 2022
Author: Maryam Moghadas
Date: 2022-11-21T13:22:27-06:00
New Revision: bd68070481d3606e05c4bb79725d4646fb85e0ec
URL: https://github.com/llvm/llvm-project/commit/bd68070481d3606e05c4bb79725d4646fb85e0ec
DIFF: https://github.com/llvm/llvm-project/commit/bd68070481d3606e05c4bb79725d4646fb85e0ec.diff
LOG: [PowerPC] Add new load/store with length instructions to Future CPU.
This patch adds 8 news load and store with length instructions including
lxvrl, lxvrll, stxvrl, stxvrll, lxvprl, lxvprll, stxvprl, stxvprll.
Reviewed By: stefanp, amyk, saghir
Differential Revision: https://reviews.llvm.org/D136992
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrFuture.td
llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 0d3ac801f20eb..d5c7895ddc45a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -51,3 +51,38 @@ defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
"subfus", "$RT, $L, $RA, $RB", []>;
}
+let Predicates = [HasVSX, IsISAFuture] in {
+ let mayLoad = 1 in {
+ def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
+ "lxvrl $XT, $src, $rB", IIC_LdStLoad, []>;
+
+ def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
+ "lxvrll $XT, $src, $rB", IIC_LdStLoad, []>;
+
+ def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
+ (ins memr:$src, g8rc:$rB),
+ "lxvprl $XTp, $src, $rB", IIC_LdStLFD, []>;
+
+ def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
+ (ins memr:$src, g8rc:$rB),
+ "lxvprll $XTp, $src, $rB", IIC_LdStLFD, []>;
+ }
+
+ let mayStore = 1 in {
+ def STXVRL : XX1Form_memOp<31, 653, (outs),
+ (ins vsrc:$XT, memr:$dst, g8rc:$rB),
+ "stxvrl $XT, $dst, $rB", IIC_LdStLoad, []>;
+
+ def STXVRLL : XX1Form_memOp<31, 685, (outs),
+ (ins vsrc:$XT, memr:$dst, g8rc:$rB),
+ "stxvrll $XT, $dst, $rB", IIC_LdStLoad, []>;
+
+ def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
+ (ins vsrprc:$XTp, memr:$src, g8rc:$rB),
+ "stxvprl $XTp, $src, $rB", IIC_LdStLFD, []>;
+
+ def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
+ (ins vsrprc:$XTp, memr:$src, g8rc:$rB),
+ "stxvprll $XTp, $src, $rB", IIC_LdStLFD, []>;
+ }
+}
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index ceca437b3b88b..aa676185cc6f2 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -51,3 +51,27 @@
#CHECK: subfus. 3, 1, 4, 5
0x7c 0x64 0x2c 0x91
+
+#CHECK: lxvrl 1, 1, 2
+0x7c 0x21 0x14 0x1a
+
+#CHECK: lxvrll 0, 3, 4
+0x7c 0x03 0x24 0x5a
+
+#CHECK: stxvrl 2, 0, 1
+0x7c 0x40 0x0d 0x1a
+
+#CHECK: stxvrll 3, 1, 5
+0x7c 0x61 0x2d 0x5a
+
+#CHECK: lxvprl 6, 1, 5
+0x7c 0xc1 0x2c 0x9a
+
+#CHECK: lxvprll 6, 2, 1
+0x7c 0xc2 0x0c 0xda
+
+#CHECK: stxvprl 0, 1, 2
+0x7c 0x01 0x15 0x9a
+
+#CHECK: stxvprll 6, 0, 1
+0x7c 0xc0 0x0d 0xda
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 60528881125e0..827142d3f505d 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -45,3 +45,27 @@
#CHECK: subfus. 3, 1, 4, 5
0x91 0x2c 0x64 0x7c
+
+#CHECK: lxvrl 1, 1, 2
+0x1a 0x14 0x21 0x7c
+
+#CHECK: lxvrll 0, 3, 4
+0x5a 0x24 0x03 0x7c
+
+#CHECK: stxvrl 2, 0, 1
+0x1a 0x0d 0x40 0x7c
+
+#CHECK: stxvrll 3, 1, 5
+0x5a 0x2d 0x61 0x7c
+
+#CHECK: lxvprl 6, 1, 5
+0x9a 0x2c 0xc1 0x7c
+
+#CHECK: lxvprll 6, 2, 1
+0xda 0x0c 0xc2 0x7c
+
+#CHECK: stxvprl 0, 1, 2
+0x9a 0x15 0x01 0x7c
+
+#CHECK: stxvprll 6, 0, 1
+0xda 0x0d 0xc0 0x7c
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 192a570df8f31..7e4f0d8658546 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -64,3 +64,35 @@
# CHECK-BE: subfus. 3, 1, 4, 5 # encoding: [0x7c,0x64,0x2c,0x91]
# CHECK-LE: subfus. 3, 1, 4, 5 # encoding: [0x91,0x2c,0x64,0x7c]
subfus. 3, 1, 4, 5
+
+# CHECK-BE: lxvrl 1, 1, 2 # encoding: [0x7c,0x21,0x14,0x1a]
+# CHECK-LE: lxvrl 1, 1, 2 # encoding: [0x1a,0x14,0x21,0x7c]
+ lxvrl 1, 1, 2
+
+# CHECK-BE: lxvrll 0, 3, 4 # encoding: [0x7c,0x03,0x24,0x5a]
+# CHECK-LE: lxvrll 0, 3, 4 # encoding: [0x5a,0x24,0x03,0x7c]
+ lxvrll 0, 3, 4
+
+# CHECK-BE: stxvrl 2, 0, 1 # encoding: [0x7c,0x40,0x0d,0x1a]
+# CHECK-LE: stxvrl 2, 0, 1 # encoding: [0x1a,0x0d,0x40,0x7c]
+ stxvrl 2, 0, 1
+
+# CHECK-BE: stxvrll 3, 1, 5 # encoding: [0x7c,0x61,0x2d,0x5a]
+# CHECK-LE: stxvrll 3, 1, 5 # encoding: [0x5a,0x2d,0x61,0x7c]
+ stxvrll 3, 1, 5
+
+# CHECK-BE: lxvprl 6, 1, 5 # encoding: [0x7c,0xc1,0x2c,0x9a]
+# CHECK-LE: lxvprl 6, 1, 5 # encoding: [0x9a,0x2c,0xc1,0x7c]
+ lxvprl 6, 1, 5
+
+# CHECK-BE: lxvprll 6, 2, 1 # encoding: [0x7c,0xc2,0x0c,0xda]
+# CHECK-LE: lxvprll 6, 2, 1 # encoding: [0xda,0x0c,0xc2,0x7c]
+ lxvprll 6, 2, 1
+
+# CHECK-BE: stxvprl 0, 1, 2 # encoding: [0x7c,0x01,0x15,0x9a]
+# CHECK-LE: stxvprl 0, 1, 2 # encoding: [0x9a,0x15,0x01,0x7c]
+ stxvprl 0, 1, 2
+
+# CHECK-BE: stxvprll 6, 0, 1 # encoding: [0x7c,0xc0,0x0d,0xda]
+# CHECK-LE: stxvprll 6, 0, 1 # encoding: [0xda,0x0d,0xc0,0x7c]
+ stxvprll 6, 0, 1
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