[PATCH] D137940: [RISCV] Enable reduction pattern SelectICmp and SelectFCmp.

[Mel Chen via Phabricator via llvm-commits]

Mel-Chen added a comment.

In D137940#3937059 <https://reviews.llvm.org/D137940#3937059>, @reames wrote:

> LGTM
>
> Just to check, you've confirmed the actual codegen for this looks vaguely reasonable right?  I don't see anything in the IR which worries me too much, just asking for the confirmation.

Codegen looks good. 
Here is how I use to confirm codegen:

  opt -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -scalable-vectorization=on -S Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll > select-cmp-reduction.gen.ll
  llc -mtriple=riscv64 -mattr=+m,+f,+v -verify-machineinstrs -target-abi=lp64d -riscv-v-vector-bits-min=-1 < select-cmp-reduction.gen.ll > select-cmp-reduction.gen.s


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  https://reviews.llvm.org/D137940/new/

https://reviews.llvm.org/D137940