[PATCH] D137949: [RISCV] Branchless lowering for (select (x < 0), TrueConstant, FalseConstant) and (select (x >= 0), TrueConstant, FalseConstant)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9637
+      int64_t FalseSImm = cast<ConstantSDNode>(FalseV)->getSExtValue();
+      // Only handle simm12, if it is not in this range, it can be considered as
+      // register.
----------------
Can you share most of the code by adding

```
if (CCVal == ISD::CondCode::SETGE)
  std::swap(TrueImm, FalseImm)
```

And another std::swap for TrueV and FalseV if the match succeeds?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137949/new/

https://reviews.llvm.org/D137949