[PATCH] D134792: [PowerPC][GISel] support 64 bit load/store

[ChenZheng via Phabricator via llvm-commits]

shchenz marked an inline comment as done.
shchenz added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp:143
+    // Check if the store is fed by fp instructions.
+    MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
+    if (onlyDefinesFP(*DefMI, MRI, TRI))
----------------
arsenm wrote:
> shchenz wrote:
> > arsenm wrote:
> > > This call doesn't make any sense, you're just getting a pointer to MI with more steps 
> > Similar with G_LOAD. With current Generic MIR infra, on PPC, we have to know what instruction defines the operand 0 of the MI, float point or fixed point. Operand 0 is the content stored to the memory, right?
> Operand 0 is the result operand. Operand 1 is the stored value 
hmm, I dump the operands for the MI `G_STORE %1:_(s64), %0:_(p0) :: (store (s64) into %ir.p)`, the operand 0 is `%1:_(s64)`, operand 1 is `%0:_(p0)`.

the ll is:
```

define void @store_i64(i64* %p) {
entry:
  store i64 100, i64* %p, align 8
  ret void
}
```

MIR before reg bank selection is:
```
# Machine code for function store_i64: IsSSA, TracksLiveness, Legalized
Function Live Ins: $x3

bb.1.entry:
  liveins: $x3
  %0:_(p0) = COPY $x3
  %1:_(s64) = G_CONSTANT i64 100
  G_STORE %1:_(s64), %0:_(p0) :: (store (s64) into %ir.p)
  BLR8 implicit $lr8, implicit $rm

# End machine code for function store_i64.
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134792/new/

https://reviews.llvm.org/D134792