[llvm] a6cb924 - [TableGen] Let -register-info-debug dump Offset/Size for each SubRegIndex

[Bjorn Pettersson via llvm-commits]

Author: Bjorn Pettersson
Date: 2022-11-20T20:52:13+01:00
New Revision: a6cb924abcd852cc598d98936aa1c4d7c2e90845

URL: https://github.com/llvm/llvm-project/commit/a6cb924abcd852cc598d98936aa1c4d7c2e90845
DIFF: https://github.com/llvm/llvm-project/commit/a6cb924abcd852cc598d98936aa1c4d7c2e90845.diff

LOG: [TableGen] Let -register-info-debug dump Offset/Size for each SubRegIndex

This patch adds dumping of the Offset and Size info for each
SubRegIndex printed when using
  llvm-tblgen -gen-register-info -register-info-debug

It also updates the ConcatenatedSubregs.td to check those printouts,
including some new subreg definitions that show short-comings in
how the size is calculated when concatenating subregisters and at
least one has an incomplete size (-1). Today TableGen will just add
sizes together, resulting in MCRegisterInfo::getSubRegIdxSize()
returning a value that isn't -1 even if the combined subregister size
is unknown.

Differential Revision: https://reviews.llvm.org/D138340

Added: 
    

Modified: 
    llvm/test/TableGen/ConcatenatedSubregs.td
    llvm/utils/TableGen/RegisterInfoEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/ConcatenatedSubregs.td b/llvm/test/TableGen/ConcatenatedSubregs.td
index 1e6c22b071ec5..87db95949b78c 100644
--- a/llvm/test/TableGen/ConcatenatedSubregs.td
+++ b/llvm/test/TableGen/ConcatenatedSubregs.td
@@ -23,7 +23,7 @@ def sub0 : SubRegIndex<32>;
 def sub1 : SubRegIndex<32, 32>;
 def sub2 : SubRegIndex<32, 64>;
 
-def ssub0 : SubRegIndex<16>;
+def ssub0 : SubRegIndex<-1>;
 def ssub1 : SubRegIndex<16, 16>;
 def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
 def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
@@ -57,6 +57,7 @@ def D5 : MyReg<"d5", [S10, S11]>;
 def D6 : MyReg<"d6", [S12, S13]>;
 def D7 : MyReg<"d7", [S14, S15]>;
 }
+
 def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 7)>;
 
 def Dtup2regs : RegisterTuples<[sub0, sub1],
@@ -88,14 +89,20 @@ def TestTarget : Target;
 // CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
 // CHECK-LABEL: RegisterClass DRegs:
 
+// CHECK-LABEL: SubRegIndex ssub1:
+// CHECK:        Offset, Size: 16, 16
 // CHECK-LABEL: SubRegIndex sub0:
 // CHECK-LABEL: SubRegIndex sub1:
 // CHECK-LABEL: SubRegIndex sub2:
 // Check inferred indexes:
-// CHECK: SubRegIndex ssub1_ssub2:
-// CHECK: SubRegIndex ssub3_ssub4:
-// CHECK: SubRegIndex ssub0_ssub1_ssub2_ssub3:
-// CHECK: SubRegIndex ssub1_ssub2_ssub3_ssub4:
+// CHECK-LABEL: SubRegIndex ssub1_ssub2:
+// FIXME: Size should be unknown (65535).
+// CHECK:         Offset, Size: 16, 15
+// CHECK-LABEL: SubRegIndex ssub3_ssub4:
+// CHECK-LABEL: SubRegIndex ssub0_ssub1_ssub2_ssub3:
+// FIXME: Size should be unknown (65535).
+// CHECK:         Offset, Size: 65535, 30
+// CHECK-LABEL: SubRegIndex ssub1_ssub2_ssub3_ssub4:
 
 // Check that all subregs are generated on some examples
 // CHECK-LABEL: Register D0:

diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 971ebb710af23..4d75d3020383e 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1836,6 +1836,7 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
     OS << "SubRegIndex " << SRI.getName() << ":\n";
     OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';
     OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';
+    OS << "\tOffset, Size: " << SRI.Offset << ", " << SRI.Size << '\n';
   }
 
   for (const CodeGenRegister &R : RegBank.getRegisters()) {