[PATCH] D138379: [VP][RISCV] Add vp.fshl/fshr and RISC-V support.

[Yeting Kuo via Phabricator via llvm-commits]

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The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138379

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/IR/VPIntrinsics.def
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
  llvm/unittests/IR/VPIntrinsicTest.cpp

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