[llvm] 611db1c - [X86] Remove unnecessary bit test instruction overrides from znver2 model

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-11-20T12:22:11Z
New Revision: 611db1c78fcbbe5de633101006dc5c4c087b72cb

URL: https://github.com/llvm/llvm-project/commit/611db1c78fcbbe5de633101006dc5c4c087b72cb
DIFF: https://github.com/llvm/llvm-project/commit/611db1c78fcbbe5de633101006dc5c4c087b72cb.diff

LOG: [X86] Remove unnecessary bit test instruction overrides from znver2 model

Reported by D138359 and confirmed with AMD SoG - matches znver1 model

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleZnver2.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index 04286560c0bb..90b66d264802 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -706,18 +706,7 @@ def Zn2WriteALULat2Ld : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
   let Latency = 6;
 }
 
-// BT.
-// m,i.
-def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
-
 // BTR BTS BTC.
-// r,r,i.
-def Zn2WriteBTRSC : SchedWriteRes<[Zn2ALU]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-}
-def : InstRW<[Zn2WriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
-
 // m,r,i.
 def Zn2WriteBTRSCm : SchedWriteRes<[Zn2AGU, Zn2ALU]> {
   let Latency = 6;