[PATCH] D87704: [AMDGPU] Reduce stack pointer alignment

[Matt Arsenault via Phabricator via llvm-commits]

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I think this should be abandoned. Requiring 16-byte stack alignment doesn't require 16-byte alignment for a VGPR spill. The spill alignment requirement is only 4. This mostly matters for when stack realignment is necessary. The stack waste comes only in call frame contexts


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https://reviews.llvm.org/D87704