[llvm] 1fe1299 - GlobalISel: Legalize strict_fsub
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 18 15:21:47 PST 2022
Author: Matt Arsenault
Date: 2022-11-18T15:21:41-08:00
New Revision: 1fe1299a93e1001455cb5088ed2cac87967f0029
URL: https://github.com/llvm/llvm-project/commit/1fe1299a93e1001455cb5088ed2cac87967f0029
DIFF: https://github.com/llvm/llvm-project/commit/1fe1299a93e1001455cb5088ed2cac87967f0029.diff
LOG: GlobalISel: Legalize strict_fsub
In the future should probably have a more convenient
way to switch between building strict and non-strict ops.
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
Modified:
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index d9f37971840a5..3c1332c23286c 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1677,6 +1677,13 @@ class MachineIRBuilder {
return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
}
+ /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
+ MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0,
+ const SrcOp &Src1,
+ Optional<unsigned> Flags = None) {
+ return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
+ }
+
/// Build and insert \p Res = G_FSUB \p Op0, \p Op1
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
const SrcOp &Src1,
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index b8460f156a8f2..6ea4f6c9ac109 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3319,7 +3319,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
MI.eraseFromParent();
return Legalized;
}
- case TargetOpcode::G_FSUB: {
+ case TargetOpcode::G_FSUB:
+ case TargetOpcode::G_STRICT_FSUB: {
Register Res = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Res);
@@ -3330,9 +3331,13 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return UnableToLegalize;
Register LHS = MI.getOperand(1).getReg();
Register RHS = MI.getOperand(2).getReg();
- Register Neg = MRI.createGenericVirtualRegister(Ty);
- MIRBuilder.buildFNeg(Neg, RHS);
- MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
+ auto Neg = MIRBuilder.buildFNeg(Ty, RHS);
+
+ if (MI.getOpcode() == TargetOpcode::G_STRICT_FSUB)
+ MIRBuilder.buildStrictFAdd(Res, LHS, Neg, MI.getFlags());
+ else
+ MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
+
MI.eraseFromParent();
return Legalized;
}
@@ -4219,6 +4224,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case G_SADDE:
case G_SSUBE:
case G_STRICT_FADD:
+ case G_STRICT_FSUB:
case G_STRICT_FMUL:
case G_STRICT_FMA:
return fewerElementsVectorMultiEltType(GMI, NumElts);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index e4cc2a6b73af6..a6088cd908502 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -795,7 +795,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.narrowScalarFor({{S64, S16}}, changeTo(0, S32))
.scalarize(0);
- auto &FSubActions = getActionDefinitionsBuilder(G_FSUB);
+ auto &FSubActions = getActionDefinitionsBuilder({G_FSUB, G_STRICT_FSUB});
if (ST.has16BitInsts()) {
FSubActions
// Use actual fsub instruction
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
new file mode 100644
index 0000000000000..aeec40ab4aac4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name: test_strict_fsub_s64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; GCN-LABEL: name: test_strict_fsub_s64
+ ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GCN-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
+ ; GCN-NEXT: [[STRICT_FADD:%[0-9]+]]:_(s64) = G_STRICT_FADD [[COPY]], [[FNEG]]
+ ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[STRICT_FADD]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_STRICT_FSUB %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_strict_fsub_v2s16
+body: |
+ bb.0.entry:
+ liveins: $vgpr0, $vgpr1
+
+ ; GCN-LABEL: name: test_strict_fsub_v2s16
+ ; GCN: liveins: $vgpr0, $vgpr1
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+ ; GCN-NEXT: [[FNEG:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[COPY1]]
+ ; GCN-NEXT: [[STRICT_FADD:%[0-9]+]]:_(<2 x s16>) = G_STRICT_FADD [[COPY]], [[FNEG]]
+ ; GCN-NEXT: $vgpr0 = COPY [[STRICT_FADD]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = COPY $vgpr1
+ %2:_(<2 x s16>) = G_STRICT_FSUB %0, %1
+ $vgpr0 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
index 44aa728a728c4..df8bfcf7a819b 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
@@ -1,8 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
+
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10-GISEL %s
+
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL %s
+
; FIXME: promotion not handled without f16 insts
define half @v_constained_fsub_f16_fpexcept_strict(half %x, half %y) #0 {
@@ -57,225 +65,416 @@ define half @v_constained_fsub_f16_fpexcept_maytrap(half %x, half %y) #0 {
}
define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x half> %y) #0 {
-; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX8-GISEL-NEXT: v_add_f16_e32 v2, v0, v1
+; GFX8-GISEL-NEXT: v_add_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 16
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX10PLUS-SDAG: ; %bb.0:
+; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v2, v3, v2
+; GFX10PLUS-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
+; GFX10PLUS-GISEL: ; %bb.0:
+; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10PLUS-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <2 x half> %val
}
define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x half> %y) #0 {
-; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX8-GISEL-NEXT: v_add_f16_e32 v2, v0, v1
+; GFX8-GISEL-NEXT: v_add_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 16
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX10PLUS-SDAG: ; %bb.0:
+; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v2, v3, v2
+; GFX10PLUS-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
+; GFX10PLUS-GISEL: ; %bb.0:
+; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10PLUS-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret <2 x half> %val
}
define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x half> %y) #0 {
-; GFX9-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_sub_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_sub_f16_e32 v2, v3, v2
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-SDAG-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX8-GISEL-NEXT: v_add_f16_e32 v2, v0, v1
+; GFX8-GISEL-NEXT: v_add_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 16
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-SDAG-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX10PLUS-SDAG: ; %bb.0:
+; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v0, v0, v1
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v2, v3, v2
+; GFX10PLUS-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
+; GFX10PLUS-GISEL: ; %bb.0:
+; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-GISEL-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
+; GFX10PLUS-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
ret <2 x half> %val
}
define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x half> %y) #0 {
-; GFX9-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX10-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX11-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX11-NEXT: v_sub_f16_e32 v2, v5, v4
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-SDAG-NEXT: v_perm_b32 v0, v4, v0, s4
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
+; GFX9-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-GISEL-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX9-GISEL-NEXT: v_perm_b32 v0, v0, v4, s4
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
+; GFX8-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-GISEL-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: v_bfe_u32 v1, v1, 0, 16
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-SDAG-NEXT: v_sub_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10-SDAG-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
+; GFX10-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_perm_b32 v0, v0, v4, 0x5040100
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX10PLUS-SDAG: ; %bb.0:
+; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v2, v5, v4
+; GFX10PLUS-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
+; GFX10PLUS-GISEL: ; %bb.0:
+; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX10PLUS-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v2, v4, v5
+; GFX10PLUS-GISEL-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <3 x half> @llvm.experimental.constrained.fsub.v3f16(<3 x half> %x, <3 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <3 x half> %val
}
; FIXME: Scalarized
define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y) #0 {
-; GFX9-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX9-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v5, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v4, v1, s4
-; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX8-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX10-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_sub_f16_e32 v1, v1, v3
-; GFX11-NEXT: v_sub_f16_e32 v0, v0, v2
-; GFX11-NEXT: v_sub_f16_e32 v2, v6, v5
-; GFX11-NEXT: v_sub_f16_e32 v3, v7, v4
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-SDAG-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-SDAG-NEXT: v_perm_b32 v0, v5, v0, s4
+; GFX9-SDAG-NEXT: v_perm_b32 v1, v4, v1, s4
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
+; GFX9-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v1, v3
+; GFX9-GISEL-NEXT: v_sub_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-GISEL-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-GISEL-NEXT: v_perm_b32 v0, v0, v4, s4
+; GFX9-GISEL-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v5
+; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
+; GFX8-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_sub_f16_e32 v2, v1, v3
+; GFX8-GISEL-NEXT: v_sub_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v3, 16
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-SDAG-NEXT: v_sub_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-SDAG-NEXT: v_sub_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10-SDAG-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
+; GFX10-SDAG-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-GISEL-NEXT: v_sub_f16_e32 v4, v0, v2
+; GFX10-GISEL-NEXT: v_sub_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_sub_f16_e32 v2, v1, v3
+; GFX10-GISEL-NEXT: v_sub_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-GISEL-NEXT: v_perm_b32 v0, v0, v4, 0x5040100
+; GFX10-GISEL-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX10PLUS-SDAG: ; %bb.0:
+; GFX10PLUS-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX10PLUS-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v2, v6, v5
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e32 v3, v7, v4
+; GFX10PLUS-SDAG-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-SDAG-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
+; GFX10PLUS-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
+; GFX10PLUS-GISEL: ; %bb.0:
+; GFX10PLUS-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX10PLUS-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX10PLUS-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX10PLUS-GISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v0, v0, v2
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v1, v1, v3
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v2, v4, v6
+; GFX10PLUS-GISEL-NEXT: v_sub_f16_e32 v3, v5, v7
+; GFX10PLUS-GISEL-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
+; GFX10PLUS-GISEL-NEXT: v_perm_b32 v1, v3, v1, 0x5040100
+; GFX10PLUS-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call <4 x half> @llvm.experimental.constrained.fsub.v4f16(<4 x half> %x, <4 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <4 x half> %val
}
@@ -296,38 +495,81 @@ define amdgpu_ps half @s_constained_fsub_f16_fpexcept_strict(half inreg %x, half
}
define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half> inreg %x, <2 x half> inreg %y) #0 {
-; GFX9-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s0, s3, 16
-; GFX9-NEXT: s_lshr_b32 s1, s2, 16
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_sub_f16_e32 v0, s1, v0
-; GFX9-NEXT: v_sub_f16_e32 v1, s2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshr_b32 s0, s3, 16
-; GFX8-NEXT: s_lshr_b32 s1, s2, 16
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_sub_f16_e32 v1, s2, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX10PLUS-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: v_sub_f16_e64 v0, s2, s3
-; GFX10PLUS-NEXT: s_lshr_b32 s0, s3, 16
-; GFX10PLUS-NEXT: s_lshr_b32 s1, s2, 16
-; GFX10PLUS-NEXT: v_sub_f16_e64 v1, s1, s0
-; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10PLUS-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX10PLUS-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX9-SDAG-NEXT: s_lshr_b32 s1, s2, 16
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v0, s1, v0
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, s2, v1
+; GFX9-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX9-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_xor_b32 s0, s3, 0x80008000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-GISEL-NEXT: v_pk_add_f16 v0, s2, v0
+; GFX9-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX8-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX8-SDAG-NEXT: s_lshr_b32 s1, s2, 16
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-SDAG-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-SDAG-NEXT: v_sub_f16_e32 v1, s2, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_xor_b32 s0, s3, 0x80008000
+; GFX8-GISEL-NEXT: s_lshr_b32 s3, s0, 16
+; GFX8-GISEL-NEXT: s_lshr_b32 s1, s2, 16
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-GISEL-NEXT: v_add_f16_e32 v1, s1, v1
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-GISEL-NEXT: v_add_f16_e32 v0, s2, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX10-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: v_sub_f16_e64 v0, s2, s3
+; GFX10-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX10-SDAG-NEXT: s_lshr_b32 s1, s2, 16
+; GFX10-SDAG-NEXT: v_sub_f16_e64 v1, s1, s0
+; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-SDAG-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX10-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_xor_b32 s0, s3, 0x80008000
+; GFX10-GISEL-NEXT: v_pk_add_f16 v0, s2, s0
+; GFX10-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX10PLUS-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX10PLUS-SDAG: ; %bb.0:
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e64 v0, s2, s3
+; GFX10PLUS-SDAG-NEXT: s_lshr_b32 s0, s3, 16
+; GFX10PLUS-SDAG-NEXT: s_lshr_b32 s1, s2, 16
+; GFX10PLUS-SDAG-NEXT: v_sub_f16_e64 v1, s1, s0
+; GFX10PLUS-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10PLUS-SDAG-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10PLUS-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX10PLUS-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict:
+; GFX10PLUS-GISEL: ; %bb.0:
+; GFX10PLUS-GISEL-NEXT: s_xor_b32 s0, s3, 0x80008000
+; GFX10PLUS-GISEL-NEXT: v_pk_add_f16 v0, s2, s0
+; GFX10PLUS-GISEL-NEXT: ; return to shader part epilog
%val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret <2 x half> %val
}
@@ -339,3 +581,6 @@ declare <4 x half> @llvm.experimental.constrained.fsub.v4f16(<4 x half>, <4 x ha
attributes #0 = { strictfp }
attributes #1 = { inaccessiblememonly nounwind willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX8: {{.*}}
+; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
index efa8b79e3dc04..fd73c579a87c8 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
@@ -1,7 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
+
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+
+; RUN: llc -global-isel= -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define float @v_constained_fsub_f32_fpexcept_strict(float %x, float %y) #0 {
; GCN-LABEL: v_constained_fsub_f32_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
index 6d48fbcb8cb69..4dc25ae28ebe7 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
@@ -1,7 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
define double @v_constained_fsub_f64_fpexcept_strict(double %x, double %y) #0 {
; GCN-LABEL: v_constained_fsub_f64_fpexcept_strict:
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