[llvm] c346cc3 - [Hexagon] Remove non-existent instructions

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2022-11-18T13:53:34-08:00
New Revision: c346cc3041da920e6733d7dd7328f578d2298d32

URL: https://github.com/llvm/llvm-project/commit/c346cc3041da920e6733d7dd7328f578d2298d32
DIFF: https://github.com/llvm/llvm-project/commit/c346cc3041da920e6733d7dd7328f578d2298d32.diff

LOG: [Hexagon] Remove non-existent instructions

Some instructions that don't actually exist in hardware were emitted
by the generator script in error. Delete them from the .td files.

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
    llvm/lib/Target/Hexagon/HexagonDepMappings.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
index 636e155e21807..15f5e4407f929 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -13809,18 +13809,6 @@ tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
 let isPseudo = 1;
 let isCodeGenOnly = 1;
 }
-def L6_linecpy : HInst<
-(outs DoubleRegs:$Rdd32),
-(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
-"$Rdd32 = linecpy($Rs32,$Rtt32)",
-tc_8f36a2fd, TypeLD>, Enc_fc4562, Requires<[HasV73]> {
-let Inst{7-5} = 0b001;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b10011001111;
-let mayLoad = 1;
-let isSolo = 1;
-let mayStore = 1;
-}
 def L6_memcpy : HInst<
 (outs),
 (ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
@@ -13832,33 +13820,6 @@ let mayLoad = 1;
 let isSolo = 1;
 let mayStore = 1;
 }
-def L6_movlen : HInst<
-(outs IntRegs:$Rd32),
-(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
-"$Rd32 = movlen($Rs32,$Rtt32)",
-tc_5a4b5e58, TypeCR>, Enc_80296d, Requires<[HasV73]> {
-let Inst{7-5} = 0b010;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b01101111111;
-let hasNewValue = 1;
-let opNewValue = 0;
-let isSolo = 1;
-}
-def L6_pmemcpy : HInst<
-(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, DoubleRegs:$Rtt32),
-"$Rdd32 = pmemcpy($Rx32,$Rtt32)",
-tc_af6af259, TypeLD>, Enc_c89067, Requires<[HasV73]> {
-let Inst{7-5} = 0b000;
-let Inst{13-13} = 0b0;
-let Inst{31-21} = 0b10011001111;
-let hasNewValue = 1;
-let opNewValue = 1;
-let mayLoad = 1;
-let isSolo = 1;
-let mayStore = 1;
-let Constraints = "$Rx32 = $Rx32in";
-}
 def L6_return_map_to_raw : HInst<
 (outs),
 (ins),
@@ -28779,64 +28740,6 @@ let BaseOpcode = "V6_vL32b_tmp_ppu";
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vL64b_ai : HInst<
-(outs HvxWR:$Vdd32),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii),
-"$Vdd32 = vmem($Rt32+#$Ii)",
-tc_0390c1ca, TypeCVI_VM_LD>, Enc_634460, Requires<[UseHVXV73]> {
-let Inst{7-5} = 0b011;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = BaseImmOffset;
-let accessSize = HVXVectorAccess;
-let isCVLoad = 1;
-let isCVI = 1;
-let isHVXALU = 1;
-let mayLoad = 1;
-let isRestrictNoSlot1Store = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vL64b_pi : HInst<
-(outs HvxWR:$Vdd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
-"$Vdd32 = vmem($Rx32++#$Ii)",
-tc_9a1cab75, TypeCVI_VM_LD>, Enc_5eb169, Requires<[UseHVXV73]> {
-let Inst{7-5} = 0b011;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = HVXVectorAccess;
-let isCVLoad = 1;
-let isCVI = 1;
-let isHVXALU = 1;
-let mayLoad = 1;
-let isRestrictNoSlot1Store = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vL64b_ppu : HInst<
-(outs HvxWR:$Vdd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2),
-"$Vdd32 = vmem($Rx32++$Mu2)",
-tc_9a1cab75, TypeCVI_VM_LD>, Enc_829a68, Requires<[UseHVXV73]> {
-let Inst{12-5} = 0b00000011;
-let Inst{31-21} = 0b00101011010;
-let hasNewValue = 1;
-let opNewValue = 0;
-let addrMode = PostInc;
-let accessSize = HVXVectorAccess;
-let isCVLoad = 1;
-let isCVI = 1;
-let isHVXALU = 1;
-let mayLoad = 1;
-let isRestrictNoSlot1Store = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vS32Ub_ai : HInst<
 (outs),
 (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
@@ -29945,52 +29848,6 @@ let mayStore = 1;
 let DecoderNamespace = "EXT_mmvec";
 let Constraints = "$Rx32 = $Rx32in";
 }
-def V6_vS64b_ai : HInst<
-(outs),
-(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxWR:$Vss32),
-"vmem($Rt32+#$Ii) = $Vss32",
-tc_9aff7a2a, TypeCVI_VM_ST>, Enc_b98b95, Requires<[UseHVXV73]> {
-let Inst{7-5} = 0b010;
-let Inst{12-11} = 0b00;
-let Inst{31-21} = 0b00101000011;
-let addrMode = BaseImmOffset;
-let accessSize = HVXVectorAccess;
-let isCVI = 1;
-let isHVXALU = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-}
-def V6_vS64b_pi : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxWR:$Vss32),
-"vmem($Rx32++#$Ii) = $Vss32",
-tc_227864f7, TypeCVI_VM_ST>, Enc_b025d6, Requires<[UseHVXV73]> {
-let Inst{7-5} = 0b010;
-let Inst{13-11} = 0b000;
-let Inst{31-21} = 0b00101001011;
-let addrMode = PostInc;
-let accessSize = HVXVectorAccess;
-let isCVI = 1;
-let isHVXALU = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
-def V6_vS64b_ppu : HInst<
-(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxWR:$Vss32),
-"vmem($Rx32++$Mu2) = $Vss32",
-tc_227864f7, TypeCVI_VM_ST>, Enc_046afa, Requires<[UseHVXV73]> {
-let Inst{12-5} = 0b00000010;
-let Inst{31-21} = 0b00101011011;
-let addrMode = PostInc;
-let accessSize = HVXVectorAccess;
-let isCVI = 1;
-let isHVXALU = 1;
-let mayStore = 1;
-let DecoderNamespace = "EXT_mmvec";
-let Constraints = "$Rx32 = $Rx32in";
-}
 def V6_vabs_hf : HInst<
 (outs HvxVR:$Vd32),
 (ins HvxVR:$Vu32),

diff  --git a/llvm/lib/Target/Hexagon/HexagonDepMappings.td b/llvm/lib/Target/Hexagon/HexagonDepMappings.td
index 27d3f80e926ef..7437d39eeefda 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepMappings.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepMappings.td
@@ -165,8 +165,6 @@ def V6_MAP_equwAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw H
 def V6_MAP_equw_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
 def V6_MAP_equw_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
 def V6_MAP_equw_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
-def V6_dbl_ld0Alias : InstAlias<"$Vdd32 = vmem($Rt32)", (V6_vL64b_ai HvxWR:$Vdd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
-def V6_dbl_st0Alias : InstAlias<"vmem($Rt32) = $Vss32", (V6_vS64b_ai IntRegs:$Rt32, 0, HvxWR:$Vss32)>, Requires<[UseHVX]>;
 def V6_extractw_altAlias : InstAlias<"$Rd32.w = vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
 def V6_ld0Alias : InstAlias<"$Vd32 = vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
 def V6_ldcnp0Alias : InstAlias<"if (!$Pv4) $Vd32.cur = vmem($Rt32)", (V6_vL32b_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;