[PATCH] D138323: {TableGen] RegisterInfo backend - Add abstraction layer between code generation logic and syntax output

[Rot127 via Phabricator via llvm-commits]

Rot127 added a comment.

To test the output after the refactor I used the following simple scripts:

Generate code files of all architectures.
This needs to be run twice. Once with a build on the `main` branch (remove `-new` in the output filename for this).
And once with a build with this patch (add the `-new` in the output filename again)

  #!/bin/bash
  LLVM_PATH="<path>"
  for ARCH in AArch64 AMDGPU ARC ARM AVR BPF CSKY DirectX Hexagon Lanai LoongArch M68k Mips MSP430 NVPTX PPC RISCV Sparc SPIRV SystemZ VE XCore; do
    echo $ARCH
    if [ $ARCH = "PPC" ]; then
      ARCH_D="PowerPC"
    else
      ARCH_D=$ARCH
    fi
    $LLVM_PATH/build/bin/llvm-tblgen --gen-register-info --printerLang=C++ -I $LLVM_PATH/llvm/include/ -I $LLVM_PATH/llvm/lib/Target/$ARCH_D/ -o $LLVM_PATH/tblgen-comparisons/reginfo/$ARCH-new.inc $LLVM_PATH/llvm/lib/Target/$ARCH_D/$ARCH.td
  done

Then diffing `<Arch>.inc` and `<Arch>-new.inc` with

  #!/bin/bash
  LLVM_PATH="<path>"
  for ARCH in AArch64 AMDGPU ARC ARM AVR BPF CSKY DirectX Hexagon Lanai LoongArch M68k Mips MSP430 NVPTX PPC RISCV Sparc SPIRV SystemZ VE XCore; do
    echo $ARCH
    diff $LLVM_PATH/tblgen-comparisons/reginfo/$ARCH.inc $LLVM_PATH/tblgen-comparisons/reginfo/$ARCH-new.inc
    echo $ARCH DONE
  done


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138323/new/

https://reviews.llvm.org/D138323