[llvm] 91deae9 - [MCA][X86] Add test coverage for VPCLMULQDQ instructions
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 18 13:23:21 PST 2022
Author: Simon Pilgrim
Date: 2022-11-18T21:22:10Z
New Revision: 91deae999a1ab3c195c2a464e1cdf9707e5365b6
URL: https://github.com/llvm/llvm-project/commit/91deae999a1ab3c195c2a464e1cdf9707e5365b6
DIFF: https://github.com/llvm/llvm-project/commit/91deae999a1ab3c195c2a464e1cdf9707e5365b6.diff
LOG: [MCA][X86] Add test coverage for VPCLMULQDQ instructions
Added:
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdq.s
llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdqvl.s
llvm/test/tools/llvm-mca/X86/Generic/resources-vpclmulqdq.s
llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdq.s
llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdqvl.s
llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-vpclmulqdq.s
llvm/test/tools/llvm-mca/X86/Znver3/resources-vpclmulqdq.s
Modified:
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
new file mode 100644
index 000000000000..cd834d35c43d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 1.00 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - 0.33 0.33 - 2.00 - - - - - 0.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpclmulqdq $11, (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdq.s
new file mode 100644
index 000000000000..12ac9bbc363c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdq.s
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+vpclmulqdq $11, (%rax), %zmm17, %zmm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 14 6.00 vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 20 5.67 * vpclmulqdq $11, (%rax), %zmm17, %zmm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SBDivider
+# CHECK-NEXT: [1] - SBFPDivider
+# CHECK-NEXT: [2] - SBPort0
+# CHECK-NEXT: [3] - SBPort1
+# CHECK-NEXT: [4] - SBPort4
+# CHECK-NEXT: [5] - SBPort5
+# CHECK-NEXT: [6.0] - SBPort23
+# CHECK-NEXT: [6.1] - SBPort23
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
+# CHECK-NEXT: - - 11.67 11.67 - 11.67 0.50 0.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
+# CHECK-NEXT: - - 6.00 6.00 - 6.00 - - vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: - - 5.67 5.67 - 5.67 0.50 0.50 vpclmulqdq $11, (%rax), %zmm17, %zmm19
diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdqvl.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdqvl.s
new file mode 100644
index 000000000000..f4dcb63aa332
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vpclmulqdqvl.s
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+vpclmulqdq $11, (%rax), %xmm17, %xmm19
+
+vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+vpclmulqdq $11, (%rax), %ymm17, %ymm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 14 6.00 vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 20 5.67 * vpclmulqdq $11, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 14 6.00 vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 20 5.67 * vpclmulqdq $11, (%rax), %ymm17, %ymm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SBDivider
+# CHECK-NEXT: [1] - SBFPDivider
+# CHECK-NEXT: [2] - SBPort0
+# CHECK-NEXT: [3] - SBPort1
+# CHECK-NEXT: [4] - SBPort4
+# CHECK-NEXT: [5] - SBPort5
+# CHECK-NEXT: [6.0] - SBPort23
+# CHECK-NEXT: [6.1] - SBPort23
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
+# CHECK-NEXT: - - 23.33 23.33 - 23.33 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
+# CHECK-NEXT: - - 6.00 6.00 - 6.00 - - vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: - - 5.67 5.67 - 5.67 0.50 0.50 vpclmulqdq $11, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - 6.00 6.00 - 6.00 - - vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: - - 5.67 5.67 - 5.67 0.50 0.50 vpclmulqdq $11, (%rax), %ymm17, %ymm19
diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-vpclmulqdq.s
new file mode 100644
index 000000000000..0e3739cac04b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-vpclmulqdq.s
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 14 6.00 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 1 20 5.67 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SBDivider
+# CHECK-NEXT: [1] - SBFPDivider
+# CHECK-NEXT: [2] - SBPort0
+# CHECK-NEXT: [3] - SBPort1
+# CHECK-NEXT: [4] - SBPort4
+# CHECK-NEXT: [5] - SBPort5
+# CHECK-NEXT: [6.0] - SBPort23
+# CHECK-NEXT: [6.1] - SBPort23
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
+# CHECK-NEXT: - - 11.67 11.67 - 11.67 0.50 0.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
+# CHECK-NEXT: - - 6.00 6.00 - 6.00 - - vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - 5.67 5.67 - 5.67 0.50 0.50 vpclmulqdq $11, (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdq.s
new file mode 100644
index 000000000000..0c475f5f9554
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdq.s
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+vpclmulqdq $11, (%rax), %zmm17, %zmm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 1.00 vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vpclmulqdq $11, (%rax), %zmm17, %zmm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ICXDivider
+# CHECK-NEXT: [1] - ICXFPDivider
+# CHECK-NEXT: [2] - ICXPort0
+# CHECK-NEXT: [3] - ICXPort1
+# CHECK-NEXT: [4] - ICXPort2
+# CHECK-NEXT: [5] - ICXPort3
+# CHECK-NEXT: [6] - ICXPort4
+# CHECK-NEXT: [7] - ICXPort5
+# CHECK-NEXT: [8] - ICXPort6
+# CHECK-NEXT: [9] - ICXPort7
+# CHECK-NEXT: [10] - ICXPort8
+# CHECK-NEXT: [11] - ICXPort9
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
+# CHECK-NEXT: - - - - 0.50 0.50 - 2.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# CHECK-NEXT: - - - - - - - 1.00 - - - - vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: - - - - 0.50 0.50 - 1.00 - - - - vpclmulqdq $11, (%rax), %zmm17, %zmm19
diff --git a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdqvl.s b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdqvl.s
new file mode 100644
index 000000000000..0bd0a32c33eb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vpclmulqdqvl.s
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+vpclmulqdq $11, (%rax), %xmm17, %xmm19
+
+vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+vpclmulqdq $11, (%rax), %ymm17, %ymm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 1.00 vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 2 12 1.00 * vpclmulqdq $11, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 6 1.00 vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 2 12 1.00 * vpclmulqdq $11, (%rax), %ymm17, %ymm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ICXDivider
+# CHECK-NEXT: [1] - ICXFPDivider
+# CHECK-NEXT: [2] - ICXPort0
+# CHECK-NEXT: [3] - ICXPort1
+# CHECK-NEXT: [4] - ICXPort2
+# CHECK-NEXT: [5] - ICXPort3
+# CHECK-NEXT: [6] - ICXPort4
+# CHECK-NEXT: [7] - ICXPort5
+# CHECK-NEXT: [8] - ICXPort6
+# CHECK-NEXT: [9] - ICXPort7
+# CHECK-NEXT: [10] - ICXPort8
+# CHECK-NEXT: [11] - ICXPort9
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
+# CHECK-NEXT: - - - - 1.00 1.00 - 4.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# CHECK-NEXT: - - - - - - - 1.00 - - - - vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: - - - - 0.50 0.50 - 1.00 - - - - vpclmulqdq $11, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - 1.00 - - - - vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: - - - - 0.50 0.50 - 1.00 - - - - vpclmulqdq $11, (%rax), %ymm17, %ymm19
diff --git a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-vpclmulqdq.s
new file mode 100644
index 000000000000..a1c5223f2bae
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-vpclmulqdq.s
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 1.00 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 12 1.00 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ICXDivider
+# CHECK-NEXT: [1] - ICXFPDivider
+# CHECK-NEXT: [2] - ICXPort0
+# CHECK-NEXT: [3] - ICXPort1
+# CHECK-NEXT: [4] - ICXPort2
+# CHECK-NEXT: [5] - ICXPort3
+# CHECK-NEXT: [6] - ICXPort4
+# CHECK-NEXT: [7] - ICXPort5
+# CHECK-NEXT: [8] - ICXPort6
+# CHECK-NEXT: [9] - ICXPort7
+# CHECK-NEXT: [10] - ICXPort8
+# CHECK-NEXT: [11] - ICXPort9
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
+# CHECK-NEXT: - - - - 0.50 0.50 - 2.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# CHECK-NEXT: - - - - - - - 1.00 - - - - vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - 0.50 0.50 - 1.00 - - - - vpclmulqdq $11, (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-vpclmulqdq.s
new file mode 100644
index 000000000000..31680d562a42
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-vpclmulqdq.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver3 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 4 4 2.00 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 4 11 2.00 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - Zn3AGU0
+# CHECK-NEXT: [1] - Zn3AGU1
+# CHECK-NEXT: [2] - Zn3AGU2
+# CHECK-NEXT: [3] - Zn3ALU0
+# CHECK-NEXT: [4] - Zn3ALU1
+# CHECK-NEXT: [5] - Zn3ALU2
+# CHECK-NEXT: [6] - Zn3ALU3
+# CHECK-NEXT: [7] - Zn3BRU1
+# CHECK-NEXT: [8] - Zn3FPP0
+# CHECK-NEXT: [9] - Zn3FPP1
+# CHECK-NEXT: [10] - Zn3FPP2
+# CHECK-NEXT: [11] - Zn3FPP3
+# CHECK-NEXT: [12.0] - Zn3FPP45
+# CHECK-NEXT: [12.1] - Zn3FPP45
+# CHECK-NEXT: [13] - Zn3FPSt
+# CHECK-NEXT: [14.0] - Zn3LSU
+# CHECK-NEXT: [14.1] - Zn3LSU
+# CHECK-NEXT: [14.2] - Zn3LSU
+# CHECK-NEXT: [15.0] - Zn3Load
+# CHECK-NEXT: [15.1] - Zn3Load
+# CHECK-NEXT: [15.2] - Zn3Load
+# CHECK-NEXT: [16.0] - Zn3Store
+# CHECK-NEXT: [16.1] - Zn3Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1]
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpclmulqdq $11, (%rax), %ymm1, %ymm3
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