[PATCH] D137593: [RISCV] Optimize scalable frame setup when VLEN is precisely known

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:386
+    // 1. Multiply the number of v-slots by the (constant) length of register
+    Register ScratchReg =
+      MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
----------------
Move vreg creation to line 402?


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Comment at: llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll:90
 ; SPILL-O2-VLEN128-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; SPILL-O2-VLEN128-NEXT:    csrr a1, vlenb
-; SPILL-O2-VLEN128-NEXT:    slli a1, a1, 1
-; SPILL-O2-VLEN128-NEXT:    sub sp, sp, a1
+; SPILL-O2-VLEN128-NEXT:    sub sp, sp, 512
 ; SPILL-O2-VLEN128-NEXT:    mv s0, a0
----------------
This instruction doesn't exist. You need addi sp, sp, -512


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Comment at: llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll:107
 ; SPILL-O2-VLEN128-NEXT:    vfadd.vv v8, v9, v8
-; SPILL-O2-VLEN128-NEXT:    csrr a0, vlenb
-; SPILL-O2-VLEN128-NEXT:    slli a0, a0, 1
-; SPILL-O2-VLEN128-NEXT:    add sp, sp, a0
+; SPILL-O2-VLEN128-NEXT:    add sp, sp, 512
 ; SPILL-O2-VLEN128-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
----------------
addi sp, sp, 512


Repository:
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  https://reviews.llvm.org/D137593/new/

https://reviews.llvm.org/D137593