[llvm] 38302c6 - [AMDGPU] Stop looking for implicit M0 uses on MOV instructions
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 18 09:00:20 PST 2022
Author: Jay Foad
Date: 2022-11-18T16:57:55Z
New Revision: 38302c60efe520e2cf1749d6e1ac23648dcad5ee
URL: https://github.com/llvm/llvm-project/commit/38302c60efe520e2cf1749d6e1ac23648dcad5ee
DIFF: https://github.com/llvm/llvm-project/commit/38302c60efe520e2cf1749d6e1ac23648dcad5ee.diff
LOG: [AMDGPU] Stop looking for implicit M0 uses on MOV instructions
Before D114230, indirect moves used regular MOV opcodes and were
identified by having an implicit use of M0. Since D114230 they use
dedicated opcodes instead, so remove some old code that checks for
implicit uses of M0. NFCI.
Differential Revision: https://reviews.llvm.org/D138308
Added:
Modified:
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index f571bcda94f8..979f335d770c 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -449,24 +449,10 @@ bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
return true;
}
-// If the use operand doesn't care about the value, this may be an operand only
-// used for register indexing, in which case it is unsafe to fold.
bool SIFoldOperands::isUseSafeToFold(const MachineInstr &MI,
const MachineOperand &UseMO) const {
- if (UseMO.isUndef() || TII->isSDWA(MI))
- return false;
-
- switch (MI.getOpcode()) {
- case AMDGPU::V_MOV_B32_e32:
- case AMDGPU::V_MOV_B32_e64:
- case AMDGPU::V_MOV_B64_PSEUDO:
- case AMDGPU::V_MOV_B64_e32:
- case AMDGPU::V_MOV_B64_e64:
- // Do not fold into an indirect mov.
- return !MI.hasRegisterImplicitUseOperand(AMDGPU::M0);
- }
-
- return true;
+ // Operands of SDWA instructions must be registers.
+ return !TII->isSDWA(MI);
}
// Find a def of the UseReg, check if it is a reg_sequence and find initializers
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index c54d23ee40f3..0e01d93e1100 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -637,9 +637,6 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
if (!TRI->isVGPR(*MRI, X))
return nullptr;
- if (MovT.hasRegisterImplicitUseOperand(AMDGPU::M0))
- return nullptr;
-
const unsigned SearchLimit = 16;
unsigned Count = 0;
bool KilledT = false;
@@ -654,8 +651,7 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
MovY->getOpcode() != AMDGPU::COPY) ||
!MovY->getOperand(1).isReg() ||
MovY->getOperand(1).getReg() != T ||
- MovY->getOperand(1).getSubReg() != Tsub ||
- MovY->hasRegisterImplicitUseOperand(AMDGPU::M0))
+ MovY->getOperand(1).getSubReg() != Tsub)
continue;
Register Y = MovY->getOperand(0).getReg();
@@ -688,9 +684,6 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
MovX = nullptr;
break;
}
- // Implicit use of M0 is an indirect move.
- if (I->hasRegisterImplicitUseOperand(AMDGPU::M0))
- continue;
if (Size > 1 && (I->getNumImplicitOperands() > (I->isCopy() ? 0U : 1U)))
continue;
diff --git a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
index 222063316d03..83c2d060d7fb 100644
--- a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
@@ -848,7 +848,7 @@ body: |
...
# GCN-LABEL: name: indirect_mov_t
-# GCN: $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec, implicit $m0
+# GCN: $vgpr2 = V_MOV_B32_indirect_read killed $vgpr0, implicit $exec, implicit $m0
# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
# GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
@@ -859,7 +859,7 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
- $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec, implicit $m0
+ $vgpr2 = V_MOV_B32_indirect_read killed $vgpr0, implicit $exec, implicit $m0
$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
@@ -867,7 +867,7 @@ body: |
# GCN-LABEL: name: indirect_mov_x
# GCN: $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
-# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec, implicit $m0
+# GCN-NEXT: $vgpr0 = V_MOV_B32_indirect_read killed $vgpr1, implicit $exec, implicit $m0
# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
# GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
@@ -878,7 +878,7 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
- $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec, implicit $m0
+ $vgpr0 = V_MOV_B32_indirect_read killed $vgpr1, implicit $exec, implicit $m0
$vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
...
@@ -886,7 +886,7 @@ body: |
# GCN-LABEL: name: indirect_mov_y
# GCN: $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
-# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec, implicit $m0
+# GCN-NEXT: $vgpr1 = V_MOV_B32_indirect_read killed $vgpr2, implicit $exec, implicit $m0
# GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
---
@@ -897,7 +897,7 @@ body: |
liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
- $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec, implicit $m0
+ $vgpr1 = V_MOV_B32_indirect_read killed $vgpr2, implicit $exec, implicit $m0
S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
...
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