[PATCH] D137940: [RISCV] Enable reduction pattern SelectICmp and SelectFCmp.

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

In D137940#3937059 <https://reviews.llvm.org/D137940#3937059>, @reames wrote:

> LGTM
>
> Just to check, you've confirmed the actual codegen for this looks vaguely reasonable right?  I don't see anything in the IR which worries me too much, just asking for the confirmation.

It does to me yeah - the output looks similar to llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll and we have the same pattern of compares/selects in the vector loop, as well as compares + or reduce in the middle block. None of the tests crash and the RISCV version bails out in the same way as AArch64 for `@select_const_f32_from_icmp`.

The tests in this patch don't test interleaving like the tests in llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll do, but I figured that they are going down the same code path by this point and wasn't sure if it would add much value being tested again here.


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https://reviews.llvm.org/D137940