[PATCH] D138288: [AArch64][SME2] Remove vector constraints from zip/uzp (2-vector) instruction classes

David Sherwood via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 18 05:12:33 PST 2022


david-arm created this revision.
david-arm added reviewers: sdesmalen, paulwalker-arm, CarolineConcatto.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
david-arm requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

The zip/uzp (2-vector) instruction classes have the incorrect
register constraints and mark the destination as also being an
input. However, the instructions are fully destructive so I've
restructured the classes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138288

Files:
  llvm/lib/Target/AArch64/SMEInstrFormats.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D138288.476433.patch
Type: text/x-patch
Size: 5333 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221118/0e9695b8/attachment.bin>


More information about the llvm-commits mailing list