[llvm] 7a715bf - [VP] Add support for vp.inttoptr & vp.ptrtoint
Yingchi Long via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 17 18:43:04 PST 2022
Author: YingChi Long
Date: 2022-11-18T10:42:24+08:00
New Revision: 7a715bf317d09264557415f6ed1d9fe930c1c2cd
URL: https://github.com/llvm/llvm-project/commit/7a715bf317d09264557415f6ed1d9fe930c1c2cd
DIFF: https://github.com/llvm/llvm-project/commit/7a715bf317d09264557415f6ed1d9fe930c1c2cd.diff
LOG: [VP] Add support for vp.inttoptr & vp.ptrtoint
Add vp.inttoptr & vp.ptrtoint support by lowering them into
vp.zext / vp.truncate with in SelectionDAGBuilder.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D137169
Added:
llvm/test/CodeGen/RISCV/rvv/fixed-vector-inttoptr-ptrtoint.ll
Modified:
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 640cb15e03c53..806659455062a 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -943,6 +943,21 @@ class SelectionDAG {
SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask,
SDValue EVL, EVT VT);
+ /// Convert a vector-predicated Op, which must be an integer vector, to the
+ /// vector-type VT, by performing either vector-predicated zext or truncating
+ /// it. The Op will be returned as-is if Op and VT are vectors containing
+ /// integer with same width.
+ SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask,
+ SDValue EVL);
+
+ /// Convert a vector-predicated Op, which must be of integer type, to the
+ /// vector-type integer type VT, by either truncating it or performing either
+ /// vector-predicated zero or sign extension as appropriate extension for the
+ /// pointer's semantics. This function just redirects to getVPZExtOrTrunc
+ /// right now.
+ SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask,
+ SDValue EVL);
+
/// Returns sum of the base pointer and offset.
/// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 8c7e975639381..3d38968a7bc3b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1482,6 +1482,20 @@ SDValue SelectionDAG::getVPLogicalNOT(const SDLoc &DL, SDValue Val,
return getNode(ISD::VP_XOR, DL, VT, Val, TrueValue, Mask, EVL);
}
+SDValue SelectionDAG::getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op,
+ SDValue Mask, SDValue EVL) {
+ return getVPZExtOrTrunc(DL, VT, Op, Mask, EVL);
+}
+
+SDValue SelectionDAG::getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op,
+ SDValue Mask, SDValue EVL) {
+ if (VT.bitsGT(Op.getValueType()))
+ return getNode(ISD::VP_ZERO_EXTEND, DL, VT, Op, Mask, EVL);
+ if (VT.bitsLT(Op.getValueType()))
+ return getNode(ISD::VP_TRUNCATE, DL, VT, Op, Mask, EVL);
+ return Op;
+}
+
SDValue SelectionDAG::getBoolConstant(bool V, const SDLoc &DL, EVT VT,
EVT OpVT) {
if (!V)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index baf97329a6213..fe7d6b363e7a8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7704,6 +7704,30 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
}
break;
}
+ case ISD::VP_INTTOPTR: {
+ SDValue N = OpValues[0];
+ EVT DestVT = TLI.getValueType(DAG.getDataLayout(), VPIntrin.getType());
+ EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(), VPIntrin.getType());
+ N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1],
+ OpValues[2]);
+ N = DAG.getVPZExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1],
+ OpValues[2]);
+ setValue(&VPIntrin, N);
+ break;
+ }
+ case ISD::VP_PTRTOINT: {
+ SDValue N = OpValues[0];
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
+ VPIntrin.getType());
+ EVT PtrMemVT = TLI.getMemValueType(DAG.getDataLayout(),
+ VPIntrin.getOperand(0)->getType());
+ N = DAG.getVPPtrExtOrTrunc(getCurSDLoc(), PtrMemVT, N, OpValues[1],
+ OpValues[2]);
+ N = DAG.getVPZExtOrTrunc(getCurSDLoc(), DestVT, N, OpValues[1],
+ OpValues[2]);
+ setValue(&VPIntrin, N);
+ break;
+ }
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-inttoptr-ptrtoint.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-inttoptr-ptrtoint.ll
new file mode 100644
index 0000000000000..866599fe4e25e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-inttoptr-ptrtoint.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-vector-bits-min=128 < %s \
+; RUN: | FileCheck %s
+
+declare <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i32(<4 x i32>, <4 x i1>, i32)
+
+define <4 x ptr> @inttoptr_v4p0_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: inttoptr_v4p0_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %v = call <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
+ ret <4 x ptr> %v
+}
+
+declare <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i64(<4 x i64>, <4 x i1>, i32)
+
+define <4 x ptr> @inttoptr_v4p0_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: inttoptr_v4p0_v4i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
+ %v = call <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
+ ret <4 x ptr> %v
+}
+
+declare <4 x i32> @llvm.vp.ptrtoint.v4i32.v4p0(<4 x ptr>, <4 x i1>, i32)
+
+define <4 x i32> @ptrtoint_v4i32_v4p0(<4 x ptr> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: ptrtoint_v4i32_v4p0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %v = call <4 x i32> @llvm.vp.ptrtoint.v4i32.v4p0(<4 x ptr> %va, <4 x i1> %m, i32 %evl)
+ ret <4 x i32> %v
+}
+
+declare <4 x i64> @llvm.vp.ptrtoint.v4i64.v4p0(<4 x ptr>, <4 x i1>, i32)
+
+define <4 x i64> @ptrtoint_v4i64_v4p0(<4 x ptr> %va, <4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: ptrtoint_v4i64_v4p0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
+ %v = call <4 x i64> @llvm.vp.ptrtoint.v4i64.v4p0(<4 x ptr> %va, <4 x i1> %m, i32 %evl)
+ ret <4 x i64> %v
+}
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