[llvm] 35cc9bc - [Hexagon] Add ELF flags for Hexagon v71, v71t, and v73

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2022-11-17T14:15:46-08:00
New Revision: 35cc9bc486cb51292ce4628734b4cdf01195e3e1

URL: https://github.com/llvm/llvm-project/commit/35cc9bc486cb51292ce4628734b4cdf01195e3e1
DIFF: https://github.com/llvm/llvm-project/commit/35cc9bc486cb51292ce4628734b4cdf01195e3e1.diff

LOG: [Hexagon] Add ELF flags for Hexagon v71, v71t, and v73

Added: 
    

Modified: 
    llvm/include/llvm/BinaryFormat/ELF.h
    llvm/lib/ObjectYAML/ELFYAML.cpp

Removed: 
    


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diff  --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h
index 3a3d42e8b1706..9f6b00ba4a657 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -620,6 +620,9 @@ enum {
   EF_HEXAGON_MACH_V67T = 0x00008067, // Hexagon V67T
   EF_HEXAGON_MACH_V68 = 0x00000068,  // Hexagon V68
   EF_HEXAGON_MACH_V69 = 0x00000069,  // Hexagon V69
+  EF_HEXAGON_MACH_V71 = 0x00000071,  // Hexagon V71
+  EF_HEXAGON_MACH_V71T = 0x00008071, // Hexagon V71T
+  EF_HEXAGON_MACH_V73 = 0x00000073,  // Hexagon V73
   EF_HEXAGON_MACH = 0x000003ff,      // Hexagon V..
 
   // Highest ISA version flags
@@ -637,6 +640,9 @@ enum {
   EF_HEXAGON_ISA_V67 = 0x00000067,  // Hexagon V67 ISA
   EF_HEXAGON_ISA_V68 = 0x00000068,  // Hexagon V68 ISA
   EF_HEXAGON_ISA_V69 = 0x00000069,  // Hexagon V69 ISA
+  EF_HEXAGON_ISA_V71 = 0x00000071,  // Hexagon V71 ISA
+  EF_HEXAGON_ISA_V73 = 0x00000073,  // Hexagon V73 ISA
+  EF_HEXAGON_ISA_V75 = 0x00000075,  // Hexagon V75 ISA
   EF_HEXAGON_ISA = 0x000003ff,      // Hexagon V.. ISA
 };
 

diff  --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp
index 7e95ee0849401..b94377a4e24a4 100644
--- a/llvm/lib/ObjectYAML/ELFYAML.cpp
+++ b/llvm/lib/ObjectYAML/ELFYAML.cpp
@@ -485,6 +485,9 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
     BCaseMask(EF_HEXAGON_MACH_V67T, EF_HEXAGON_MACH);
     BCaseMask(EF_HEXAGON_MACH_V68, EF_HEXAGON_MACH);
     BCaseMask(EF_HEXAGON_MACH_V69, EF_HEXAGON_MACH);
+    BCaseMask(EF_HEXAGON_MACH_V71, EF_HEXAGON_MACH);
+    BCaseMask(EF_HEXAGON_MACH_V71T, EF_HEXAGON_MACH);
+    BCaseMask(EF_HEXAGON_MACH_V73, EF_HEXAGON_MACH);
     BCaseMask(EF_HEXAGON_ISA_V2, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V3, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V4, EF_HEXAGON_ISA);
@@ -497,6 +500,8 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
     BCaseMask(EF_HEXAGON_ISA_V67, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V68, EF_HEXAGON_ISA);
     BCaseMask(EF_HEXAGON_ISA_V69, EF_HEXAGON_ISA);
+    BCaseMask(EF_HEXAGON_ISA_V71, EF_HEXAGON_ISA);
+    BCaseMask(EF_HEXAGON_ISA_V73, EF_HEXAGON_ISA);
     break;
   case ELF::EM_AVR:
     BCaseMask(EF_AVR_ARCH_AVR1, EF_AVR_ARCH_MASK);