[PATCH] D137169: [VP] Add support for vp.inttoptr & vp.ptrtoint

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1486
+SDValue SelectionDAG::getVPPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT,
+                                         ArrayRef<SDValue> Ops) {
+  return getVPZExtOrTrunc(Op, DL, VT, Ops);
----------------
Probably better to pass Mask and EVL explicitly. `Op` is the same as Ops[0]


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1492
+                                       ArrayRef<SDValue> Ops) {
+  if (VT.getVectorElementType().bitsEq(
+          Op.getValueType().getVectorElementType()))
----------------
I don't think you need to check the element type.. The number of elements should match.

Something like this looks better to me structurally.
```
if (VT.bitsGT(Op.getValueType())
  return getNode(ISD::VP_ZERO_EXTEND, DL, VT, Op, Mask, EVL);
if (VT.bitsLT(Op.getValueType())
  return getNode(ISD::VP_TRUNCATE, DL, VT, Op, Mask, EVL);
return Op;
```


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:7718
+  case ISD::VP_INTTOPTR: {
+    SDValue N = getValue(VPIntrin.getOperand(0));
+    EVT DestVT = TLI.getValueType(DAG.getDataLayout(), VPIntrin.getType());
----------------
This is OpValues[0] is it not?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:7727
+  case ISD::VP_PTRTOINT: {
+    SDValue N = getValue(VPIntrin.getOperand(0));
+    EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
----------------
Same


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137169/new/

https://reviews.llvm.org/D137169