[PATCH] D138211: [AArch64-SVE][StreamingMode]: test insert-vec-elt and vec-shuffle tests.

[hassnaaHamdi via Phabricator via llvm-commits]

hassnaa-arm updated this revision to Diff 476162.
hassnaa-arm added a comment.

Remove not related testing files.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138211/new/

https://reviews.llvm.org/D138211

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll


Index: llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define fp128 @test_streaming_compatible_register_mov(fp128 %q0, fp128 %q1) #0 {
+; CHECK-LABEL: test_streaming_compatible_register_mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  ret fp128 %q1
+}
+
+attributes #0 = { "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3691,7 +3691,12 @@
 
   if (AArch64::FPR128RegClass.contains(DestReg) &&
       AArch64::FPR128RegClass.contains(SrcReg)) {
-    if (Subtarget.hasNEON()) {
+    if (Subtarget.forceStreamingCompatibleSVE()) {
+      BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ))
+          .addReg(AArch64::Z0 + (DestReg - AArch64::Q0), RegState::Define)
+          .addReg(AArch64::Z0 + (SrcReg - AArch64::Q0))
+          .addReg(AArch64::Z0 + (SrcReg - AArch64::Q0));
+    } else if (Subtarget.hasNEON()) {
       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
           .addReg(SrcReg)
           .addReg(SrcReg, getKillRegState(KillSrc));


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