[PATCH] D138205: [AMDGPU] Add support for new LLVM vector types

[Mateja Marjanovic via Phabricator via llvm-commits]

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Add support on AMDGPU for vector types (v9i32, v10i32, v11i32, v12i32, and all those for f32).
Also add register types VReg, AReg and SReg with bit widths: 288, 320, 352, 384.


https://reviews.llvm.org/D138205

Files:
  llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
  llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/Analysis/CostModel/AMDGPU/add-sub.ll
  llvm/test/Analysis/CostModel/AMDGPU/arith-ssat.ll
  llvm/test/Analysis/CostModel/AMDGPU/arith-usat.ll
  llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
  llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
  llvm/test/Analysis/CostModel/AMDGPU/fma.ll
  llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
  llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
  llvm/test/Analysis/CostModel/AMDGPU/mul.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
  llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
  llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
  llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
  llvm/test/CodeGen/AMDGPU/function-returns.ll
  llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
  llvm/test/CodeGen/AMDGPU/kernel-args.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
  llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx11.mir
  llvm/test/CodeGen/AMDGPU/select.f16.ll
  llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
  llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
  llvm/test/MC/AMDGPU/gfx1013.s
  llvm/test/MC/AMDGPU/gfx1030_new.s
  llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
  llvm/test/MC/AMDGPU/gfx10_unsupported.s
  llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
  llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
  llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
  llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
  llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
  llvm/test/MC/Disassembler/AMDGPU/gfx1030_new.txt
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg.txt
  llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt

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