[llvm] 374d076 - [MachineCombiner][RISCV] Precommit tests for D136764

[Anton Sidorenko via llvm-commits]

Author: Anton Sidorenko
Date: 2022-11-17T12:12:46+03:00
New Revision: 374d07656357f05bd6d96e88c58ab999f5cebaef

URL: https://github.com/llvm/llvm-project/commit/374d07656357f05bd6d96e88c58ab999f5cebaef
DIFF: https://github.com/llvm/llvm-project/commit/374d07656357f05bd6d96e88c58ab999f5cebaef.diff

LOG: [MachineCombiner][RISCV] Precommit tests for D136764

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
    llvm/test/CodeGen/RISCV/machine-combiner.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
index 9965fa96e8719..42ea49a9e546f 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
@@ -84,3 +84,23 @@ define double @test_reassoc_flags2(double %a0, double %a1, double %a2, double %a
   %t2 = fadd contract nsz reassoc double %t1, %a3
   ret double %t2
 }
+
+; Verify FRM
+define double @test_fmadd(double %a0, double %a1, double %a2) {
+  ; CHECK-LABEL: name: test_fmadd
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $f10_d, $f11_d, $f12_d
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr64 = COPY $f12_d
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr64 = COPY $f10_d
+  ; CHECK-NEXT:   [[FMUL_D:%[0-9]+]]:fpr64 = contract nofpexcept FMUL_D [[COPY2]], [[COPY1]], 7, implicit $frm
+  ; CHECK-NEXT:   [[FADD_D:%[0-9]+]]:fpr64 = contract nofpexcept FADD_D [[FMUL_D]], [[COPY]], 7, implicit $frm
+  ; CHECK-NEXT:   [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D killed [[FADD_D]], [[FMUL_D]], 7, implicit $frm
+  ; CHECK-NEXT:   $f10_d = COPY [[FDIV_D]]
+  ; CHECK-NEXT:   PseudoRET implicit $f10_d
+  %t0 = fmul contract double %a0, %a1
+  %t1 = fadd contract double %t0, %a2
+  %t2 = fdiv double %t1, %t0
+  ret double %t2
+}

diff  --git a/llvm/test/CodeGen/RISCV/machine-combiner.ll b/llvm/test/CodeGen/RISCV/machine-combiner.ll
index 58e5ed9d77b8d..ca19c6bfa8ebe 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner.ll
@@ -184,3 +184,57 @@ define double @test_reassoc_fadd_flags_2(double %a0, double %a1, double %a2, dou
   %t2 = fadd double %t1, %a3
   ret double %t2
 }
+
+define double @test_fmadd1(double %a0, double %a1, double %a2, double %a3) {
+; CHECK-LABEL: test_fmadd1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.d ft0, fa0, fa1
+; CHECK-NEXT:    fadd.d ft1, ft0, fa2
+; CHECK-NEXT:    fadd.d ft0, fa3, ft0
+; CHECK-NEXT:    fadd.d fa0, ft1, ft0
+; CHECK-NEXT:    ret
+  %t0 = fmul contract double %a0, %a1
+  %t1 = fadd contract double %t0, %a2
+  %t2 = fadd contract double %a3, %t0
+  %t3 = fadd double %t1, %t2
+  ret double %t3
+}
+
+define double @test_fmadd2(double %a0, double %a1, double %a2) {
+; CHECK-LABEL: test_fmadd2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.d ft0, fa0, fa1
+; CHECK-NEXT:    fadd.d ft1, ft0, fa2
+; CHECK-NEXT:    fdiv.d fa0, ft1, ft0
+; CHECK-NEXT:    ret
+  %t0 = fmul contract double %a0, %a1
+  %t1 = fadd contract double %t0, %a2
+  %t2 = fdiv double %t1, %t0
+  ret double %t2
+}
+
+define double @test_fmsub(double %a0, double %a1, double %a2) {
+; CHECK-LABEL: test_fmsub:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.d ft0, fa0, fa1
+; CHECK-NEXT:    fsub.d ft1, ft0, fa2
+; CHECK-NEXT:    fdiv.d fa0, ft1, ft0
+; CHECK-NEXT:    ret
+  %t0 = fmul contract double %a0, %a1
+  %t1 = fsub contract double %t0, %a2
+  %t2 = fdiv double %t1, %t0
+  ret double %t2
+}
+
+define double @test_fnmsub(double %a0, double %a1, double %a2) {
+; CHECK-LABEL: test_fnmsub:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.d ft0, fa0, fa1
+; CHECK-NEXT:    fsub.d ft1, fa2, ft0
+; CHECK-NEXT:    fdiv.d fa0, ft1, ft0
+; CHECK-NEXT:    ret
+  %t0 = fmul contract double %a0, %a1
+  %t1 = fsub contract double %a2, %t0
+  %t2 = fdiv double %t1, %t0
+  ret double %t2
+}