[PATCH] D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat)

Wang Pengcheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 16 18:53:04 PST 2022


pcwang-thead updated this revision to Diff 475982.
pcwang-thead added a comment.

Update tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138101/new/

https://reviews.llvm.org/D138101

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D138101.475982.patch
Type: text/x-patch
Size: 15941 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221117/82281758/attachment.bin>


More information about the llvm-commits mailing list