[PATCH] D137937: [TableGen] Represent IntrHasSideEffects using inaccessiblemem read+write

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll:225
   store i32 %i3, i32 addrspace(1)* %i4, align 4
   tail call void @llvm.amdgcn.wave.barrier()
   br i1 %cc, label %while.cond, label %end
----------------
llvm.amdgcn.s.barrier and llvm.amdgcn.wave.barrier should both act like synchronizes without real memory effects, So I guess it should like a fence, but they're also typically emitted together with a fence


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137937/new/

https://reviews.llvm.org/D137937