[llvm] becf7b2 - [X86] Remove unnecessary override GFNI AFFINE reg-reg overrides from AlderlakeP model

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-11-16T17:46:29Z
New Revision: becf7b2259d68fa923d0d68c4264da6a5cc88183

URL: https://github.com/llvm/llvm-project/commit/becf7b2259d68fa923d0d68c4264da6a5cc88183
DIFF: https://github.com/llvm/llvm-project/commit/becf7b2259d68fa923d0d68c4264da6a5cc88183.diff

LOG: [X86] Remove unnecessary override GFNI AFFINE reg-reg overrides from AlderlakeP model

Now matches the default SchedWriteVecIMul values used for the instruction.

NOTE: The folded variant overrides are still there as the latency differs by 1cy

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86SchedAlderlakeP.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 14c46df5d1251..84eef847cbebe 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -999,9 +999,7 @@ def : InstRW<[ADLPWriteResGroup68, ReadAfterVecXLd], (instrs VGF2P8MULBYrm)>;
 def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort00_01]> {
   let Latency = 5;
 }
-def : InstRW<[ADLPWriteResGroup69], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrri$",
-                                               "^(V?)GF2P8MULBrr$",
-                                               "^VGF2P8AFFINE((INV)?)QBYrri$")>;
+def : InstRW<[ADLPWriteResGroup69], (instregex "^(V?)GF2P8MULBrr$")>;
 def : InstRW<[ADLPWriteResGroup69], (instrs VGF2P8MULBYrr)>;
 
 def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {