[PATCH] D137705: [AMDGPU] Add DAG Combine for right-shift carry add to uaddo

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3214
+    KnownBits AddLHSKnownBits = DAG.computeKnownBits(AddLHS);
+    KnownBits AddRHSKnownBits = DAG.computeKnownBits(AddRHS);
+    if (AddLHSKnownBits.countMinLeadingZeros() >= 32 &&
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Should try to short circuit the second known bits call if the first one fails the countMinLeadingZeros check


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3222
+      SDValue UADDO = DAG.getNode(ISD::UADDO, SL, {MVT::i32, MVT::i1}, {A, B});
+      // Replace the original add with (i64 (zext (uaddo ...)))
+      DAG.ReplaceAllUsesOfValueWith(
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Pierre-vh wrote:
> foad wrote:
> > This is not correct because it will lose the overflow bit. You should probably only do this if the ADD has a single use.
> Doing it if the add has a single use negates the purpose of the combine as it'll always have 2 uses in the cases we're interested in, but the second use is a trunc to i32. I've adapted the combine so it only does it when users are all truncs to i32, or the srl.
There's no point in looking for multiple TRUNCATE users. Those would have been automagically CSEd


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137705/new/

https://reviews.llvm.org/D137705