[PATCH] D137705: [AMDGPU] Add DAG Combine for right-shift carry add to uaddo

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3205
 
+  // fold (i64 (shr (add a, b), 32)) -> (uaddo a, b).overflow
+  //   iff a/b have >= 32 leading zeroes
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Pierre-vh wrote:
> arsenm wrote:
> > arsenm wrote:
> > > Should also move to generic code 
> > This is missing the extends in the input and output 
> What do you mean "generic"? Not checking the types and instead check that the shift amount is 1/2 of the type's size in bits?
Yes, and move to DAGCombiner. You then just need to check that the target UADDO is legal or it's pre-legalize 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137705/new/

https://reviews.llvm.org/D137705