[PATCH] D136051: [CodeGen] Introduce a flag to allow same cycle def-use schedule

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon added a comment.

Hi @ssarda, thanks for the test case. That helps to understand the problem. Which appears to be the following MIR,

  INLINEASM &"$0 = insert($1,#31,#1);" [attdialect], $0:[regdef], implicit-def $r7, $1:[reguse:IntRegs], %45:intregs
  %32:intregs = COPY $r7
  $r7 = COPY %32:intregs

These instructions are scheduled in the same cycle. Then, isValidSchedule rejects this because :

  // Furthermore, if a physical def/use pair is assigned to the same
  // cycle, orderDependence does not guarantee def/use ordering, so that
  // case should be considered invalid.

That means that orderDependence could reorder those instructions after pipelining?


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https://reviews.llvm.org/D136051