[PATCH] D136319: [GISel] Rework trunc/shl combine in a generic trunc/shift combine
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 16 08:46:14 PST 2022
arsenm added a comment.
Not sure why you deleted the test
================
Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:2262
-bool CombinerHelper::matchCombineTruncOfShl(
- MachineInstr &MI, std::pair<Register, Register> &MatchInfo) {
- assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
- Register DstReg = MI.getOperand(0).getReg();
- Register SrcReg = MI.getOperand(1).getReg();
- LLT DstTy = MRI.getType(DstReg);
- Register ShiftSrc;
- Register ShiftAmt;
-
- if (MRI.hasOneNonDBGUse(SrcReg) &&
- mi_match(SrcReg, MRI, m_GShl(m_Reg(ShiftSrc), m_Reg(ShiftAmt))) &&
- isLegalOrBeforeLegalizer(
- {TargetOpcode::G_SHL,
- {DstTy, getTargetLowering().getPreferredShiftAmountTy(DstTy)}})) {
- KnownBits Known = KB->getKnownBits(ShiftAmt);
- unsigned Size = DstTy.getSizeInBits();
- if (Known.countMaxActiveBits() <= Log2_32(Size)) {
- MatchInfo = std::make_pair(ShiftSrc, ShiftAmt);
- return true;
- }
- }
- return false;
+static LLT GetMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) {
+ const unsigned ShiftSize = ShiftTy.getScalarSizeInBits();
----------------
Start with lowercase letter
================
Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:2313-2316
+ // TODO: Fix truncstore combine to handle (trunc(lshr (trunc x), k)).
+ for (auto &User : MRI.use_instructions(DstReg))
+ if (User.getOpcode() == TargetOpcode::G_STORE)
+ return false;
----------------
I don't understand special casing this, I'd rather just ignore it
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136319/new/
https://reviews.llvm.org/D136319
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