[PATCH] D137547: [AArch64][SVE] Use PTRUE instruction for get_active_lane_mask intrinsic if the range is appropriate for predicator constant
Dinar Temirbulatov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 16 05:47:15 PST 2022
dtemirbulatov updated this revision to Diff 475805.
dtemirbulatov added a comment.
Add support for any range not just from 0.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137547/new/
https://reviews.llvm.org/D137547
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/active_lane_mask.ll
Index: llvm/test/CodeGen/AArch64/active_lane_mask.ll
===================================================================
--- llvm/test/CodeGen/AArch64/active_lane_mask.ll
+++ llvm/test/CodeGen/AArch64/active_lane_mask.ll
@@ -475,6 +475,38 @@
ret <2 x i1> %active.lane.mask
}
+define <vscale x 4 x i1> @lane_mask_nxv4i1_imm3() {
+; CHECK-LABEL: lane_mask_nxv4i1_imm3:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s, vl3
+; CHECK-NEXT: ret
+entry:
+ %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 3)
+ ret <vscale x 4 x i1> %active.lane.mask
+}
+
+define <vscale x 4 x i1> @lane_mask_nxv4i1_imm4() {
+; CHECK-LABEL: lane_mask_nxv4i1_imm4:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #4
+; CHECK-NEXT: whilelo p0.s, xzr, x8
+; CHECK-NEXT: ret
+entry:
+ %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 4)
+ ret <vscale x 4 x i1> %active.lane.mask
+}
+
+define <vscale x 16 x i1> @lane_mask_nxv16i1_imm10() {
+; CHECK-LABEL: lane_mask_nxv16i1_imm10:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: whilelo p0.b, xzr, x8
+; CHECK-NEXT: ret
+entry:
+ %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 10)
+ ret <vscale x 16 x i1> %active.lane.mask
+}
+
declare <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i32(i32, i32)
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32, i32)
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4748,6 +4748,21 @@
Op.getOperand(1))));
return SDValue();
}
+ case Intrinsic::aarch64_sve_whilelo: {
+ if (isa<ConstantSDNode>(Op.getOperand(1)) &&
+ isa<ConstantSDNode>(Op.getOperand(2))) {
+ int64_t MinSVEVectorSize = Subtarget->getMinSVEVectorSizeInBits()
+ ? Subtarget->getMinSVEVectorSizeInBits()
+ : 128;
+ unsigned ElementSize = 128 / Op.getValueType().getVectorMinNumElements();
+ unsigned Dist = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() -
+ cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+ if (getSVEPredPatternFromNumElements(Dist) != None &&
+ Dist < (MinSVEVectorSize / ElementSize))
+ return getPTrue(DAG, dl, Op.getValueType(), Dist);
+ }
+ return SDValue();
+ }
case Intrinsic::aarch64_sve_sunpkhi:
return DAG.getNode(AArch64ISD::SUNPKHI, dl, Op.getValueType(),
Op.getOperand(1));
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