[PATCH] D138101: [RISCV] Lower unmasked zero-stride vector load to (scalar load + splat)

[Wang Pengcheng via Phabricator via llvm-commits]

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So we have the opportunity to fold splat into .vx instruction as what
D101138 <https://reviews.llvm.org/D101138> has done. If failed, we can select zero-stride vector load
again.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138101

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll

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