[llvm] 4787a48 - AMDGPU/GlobalISel: Fix shift tests using out of bounds offsets

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-11-15T23:28:55-08:00
New Revision: 4787a48b96038ecebd86782ea72233ab12dfca03

URL: https://github.com/llvm/llvm-project/commit/4787a48b96038ecebd86782ea72233ab12dfca03
DIFF: https://github.com/llvm/llvm-project/commit/4787a48b96038ecebd86782ea72233ab12dfca03.diff

LOG: AMDGPU/GlobalISel: Fix shift tests using out of bounds offsets

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 9c491a7dede8..69bbff2bfa3f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -627,18 +627,33 @@ define i16 @v_ashr_i16(i16 %value, i16 %amount) {
   ret i16 %result
 }
 
-define i16 @v_ashr_i16_31(i16 %value) {
-; GCN-LABEL: v_ashr_i16_31:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+define i16 @v_ashr_i16_15(i16 %value) {
+; GFX6-LABEL: v_ashr_i16_15:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 15, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_ashr_i16_15:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_ashrrev_i16_e32 v0, 15, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_ashr_i16_31:
+; GFX9-LABEL: v_ashr_i16_15:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_ashr_i16_15:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_ashrrev_i16 v0, 15, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %result = ashr i16 %value, 31
+  %result = ashr i16 %value, 15
   ret i16 %result
 }
 

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index ad48f8dc6e30..191a90872416 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -604,18 +604,32 @@ define i16 @v_lshr_i16(i16 %value, i16 %amount) {
   ret i16 %result
 }
 
-define i16 @v_lshr_i16_31(i16 %value) {
-; GCN-LABEL: v_lshr_i16_31:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+define i16 @v_lshr_i16_15(i16 %value) {
+; GFX6-LABEL: v_lshr_i16_15:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_u32 v0, v0, 15, 1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_lshr_i16_15:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 15, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_lshr_i16_15:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_lshr_i16_31:
+; GFX10PLUS-LABEL: v_lshr_i16_15:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshrrev_b16 v0, 15, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %result = lshr i16 %value, 31
+  %result = lshr i16 %value, 15
   ret i16 %result
 }
 

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
index 4258b6431ec4..1e60a9a20569 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
@@ -618,18 +618,32 @@ define i16 @v_shl_i16(i16 %value, i16 %amount) {
   ret i16 %result
 }
 
-define i16 @v_shl_i16_31(i16 %value) {
-; GCN-LABEL: v_shl_i16_31:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+define i16 @v_shl_i16_15(i16 %value) {
+; GFX6-LABEL: v_shl_i16_15:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 15, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_shl_i16_15:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 15, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_shl_i16_15:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_shl_i16_31:
+; GFX10PLUS-LABEL: v_shl_i16_15:
 ; GFX10PLUS:       ; %bb.0:
 ; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_lshlrev_b16 v0, 15, v0
 ; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %result = shl i16 %value, 31
+  %result = shl i16 %value, 15
   ret i16 %result
 }