[PATCH] D137705: [AMDGPU] Add DAG Combine for right-shift carry add to uaddo

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3221
+      bool CanCombine = true;
+      for (SDNode *User : LHS->uses()) {
+        if (User == N)
----------------
arsenm wrote:
> Looking at uses is unusual and I'm not sure why you're doing it
As mentioned below, the thinking is that this transform is not profitable unless every use either only wants the overflow bit, or only wants the low 32 bits of the 64 bit result. Otherwise you might as well keep the full 64 bit add.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137705/new/

https://reviews.llvm.org/D137705