[llvm] 8ef1cc9 - [RISCV] Improve formatting of Sched lists in tablegen. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 15 19:20:20 PST 2022
Author: Craig Topper
Date: 2022-11-15T19:19:55-08:00
New Revision: 8ef1cc9894430f6c7c722c63c227d3b84bf889e9
URL: https://github.com/llvm/llvm-project/commit/8ef1cc9894430f6c7c722c63c227d3b84bf889e9
DIFF: https://github.com/llvm/llvm-project/commit/8ef1cc9894430f6c7c722c63c227d3b84bf889e9.diff
LOG: [RISCV] Improve formatting of Sched lists in tablegen. NFC
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 1b4813720d97..d770ed6ba339 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -403,112 +403,111 @@ multiclass VIndexLoadStore<list<int> EEWList> {
multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
- ReadVIALUV_UpperBound, ReadVMask]>;
+ ReadVIALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound,
- ReadVIALUX_UpperBound, ReadVMask]>;
+ ReadVIALUX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
- ReadVIALUV_UpperBound, ReadVMask]>;
+ ReadVIALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound,
- ReadVIALUX_UpperBound, ReadVMask]>;
+ ReadVIALUX_UpperBound, ReadVMask]>;
}
multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
- ReadVIALUX_UpperBound, ReadVMask]>;
+ ReadVIALUX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIWALUV_UpperBound, ReadVIWALUV_UpperBound,
- ReadVIWALUV_UpperBound, ReadVMask]>;
+ ReadVIWALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIWALUX_UpperBound, ReadVIWALUV_UpperBound,
- ReadVIWALUX_UpperBound, ReadVMask]>;
+ ReadVIWALUX_UpperBound, ReadVMask]>;
}
multiclass VMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIMulAddV_UpperBound, ReadVIMulAddV_UpperBound,
- ReadVIMulAddV_UpperBound, ReadVMask]>;
+ ReadVIMulAddV_UpperBound, ReadVMask]>;
def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIMulAddX_UpperBound, ReadVIMulAddV_UpperBound,
- ReadVIMulAddX_UpperBound, ReadVMask]>;
+ ReadVIMulAddX_UpperBound, ReadVMask]>;
}
multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIWMulAddV_UpperBound, ReadVIWMulAddV_UpperBound,
- ReadVIWMulAddV_UpperBound, ReadVMask]>;
+ ReadVIWMulAddV_UpperBound, ReadVMask]>;
def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIWMulAddX_UpperBound, ReadVIWMulAddV_UpperBound,
- ReadVIWMulAddX_UpperBound, ReadVMask]>;
+ ReadVIWMulAddX_UpperBound, ReadVMask]>;
}
multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIWMulAddX_UpperBound, ReadVIWMulAddV_UpperBound,
- ReadVIWMulAddX_UpperBound, ReadVMask]>;
+ ReadVIWMulAddX_UpperBound, ReadVMask]>;
}
multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
- Sched<[WriteVExtV_UpperBound, ReadVExtV_UpperBound,
- ReadVMask]>;
+ Sched<[WriteVExtV_UpperBound, ReadVExtV_UpperBound, ReadVMask]>;
}
multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUV_UpperBound, ReadVMask]>;
+ ReadVICALUV_UpperBound, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUX_UpperBound, ReadVMask]>;
+ ReadVICALUX_UpperBound, ReadVMask]>;
def IM : VALUmVI<funct6, opcodestr # ".vim">,
Sched<[WriteVICALUI_UpperBound, ReadVICALUV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
Sched<[WriteVIMergeV_UpperBound, ReadVIMergeV_UpperBound,
- ReadVIMergeV_UpperBound, ReadVMask]>;
+ ReadVIMergeV_UpperBound, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
Sched<[WriteVIMergeX_UpperBound, ReadVIMergeV_UpperBound,
- ReadVIMergeX_UpperBound, ReadVMask]>;
+ ReadVIMergeX_UpperBound, ReadVMask]>;
def IM : VALUmVI<funct6, opcodestr # ".vim">,
Sched<[WriteVIMergeI_UpperBound, ReadVIMergeV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUV_UpperBound, ReadVMask]>;
+ ReadVICALUV_UpperBound, ReadVMask]>;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUX_UpperBound, ReadVMask]>;
+ ReadVICALUX_UpperBound, ReadVMask]>;
}
multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUV_UpperBound]>;
+ ReadVICALUV_UpperBound]>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
- Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound
- , ReadVICALUX_UpperBound]>;
+ Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
+ ReadVICALUX_UpperBound]>;
def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>,
Sched<[WriteVICALUI_UpperBound, ReadVICALUV_UpperBound]>;
}
@@ -516,10 +515,10 @@ multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype =
multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
Sched<[WriteVICALUV_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUV_UpperBound]>;
+ ReadVICALUV_UpperBound]>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
Sched<[WriteVICALUX_UpperBound, ReadVICALUV_UpperBound,
- ReadVICALUX_UpperBound]>;
+ ReadVICALUX_UpperBound]>;
}
multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
@@ -703,82 +702,82 @@ multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVShiftV_UpperBound, ReadVShiftV_UpperBound,
- ReadVShiftV_UpperBound, ReadVMask]>;
+ ReadVShiftV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVShiftX_UpperBound, ReadVShiftV_UpperBound,
- ReadVShiftX_UpperBound, ReadVMask]>;
+ ReadVShiftX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
Sched<[WriteVShiftI_UpperBound, ReadVShiftV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVNShiftV_UpperBound, ReadVNShiftV_UpperBound,
- ReadVNShiftV_UpperBound, ReadVMask]>;
+ ReadVNShiftV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVNShiftX_UpperBound, ReadVNShiftV_UpperBound,
- ReadVNShiftX_UpperBound, ReadVMask]>;
+ ReadVNShiftX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
Sched<[WriteVNShiftI_UpperBound, ReadVNShiftV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVICmpV_UpperBound, ReadVICmpV_UpperBound,
- ReadVICmpV_UpperBound, ReadVMask]>;
+ ReadVICmpV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVICmpX_UpperBound, ReadVICmpV_UpperBound,
- ReadVICmpX_UpperBound, ReadVMask]>;
+ ReadVICmpX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
Sched<[WriteVICmpI_UpperBound, ReadVICmpV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVICmpV_UpperBound, ReadVICmpV_UpperBound,
- ReadVICmpX_UpperBound, ReadVMask]>;
+ ReadVICmpX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
Sched<[WriteVICmpI_UpperBound, ReadVICmpV_UpperBound,
- ReadVMask]>;
+ ReadVMask]>;
}
multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVICmpV_UpperBound, ReadVICmpV_UpperBound,
- ReadVICmpV_UpperBound, ReadVMask]>;
+ ReadVICmpV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
Sched<[WriteVICmpX_UpperBound, ReadVICmpV_UpperBound,
- ReadVICmpX_UpperBound, ReadVMask]>;
+ ReadVICmpX_UpperBound, ReadVMask]>;
}
multiclass VMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIMulV_UpperBound, ReadVIMulV_UpperBound,
- ReadVIMulV_UpperBound, ReadVMask]>;
+ ReadVIMulV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIMulX_UpperBound, ReadVIMulV_UpperBound,
- ReadVIMulX_UpperBound, ReadVMask]>;
+ ReadVIMulX_UpperBound, ReadVMask]>;
}
multiclass VWMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIWMulV_UpperBound, ReadVIWMulV_UpperBound,
- ReadVIWMulV_UpperBound, ReadVMask]>;
+ ReadVIWMulV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIWMulX_UpperBound, ReadVIWMulV_UpperBound,
- ReadVIWMulX_UpperBound, ReadVMask]>;
+ ReadVIWMulX_UpperBound, ReadVMask]>;
}
multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
Sched<[WriteVIDivV_UpperBound, ReadVIDivV_UpperBound,
- ReadVIDivV_UpperBound, ReadVMask]>;
+ ReadVIDivV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
Sched<[WriteVIDivX_UpperBound, ReadVIDivV_UpperBound,
- ReadVIDivX_UpperBound, ReadVMask]>;
+ ReadVIDivX_UpperBound, ReadVMask]>;
}
multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index efb11f43ddca..b320f16e9658 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2890,10 +2890,10 @@ multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
defm "" : VPseudoTernaryV_VV_AAXA_LMUL<m, Constraint>,
Sched<[WriteVIMulAddV_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
- ReadVIMulAddV_MX, ReadVMask]>;
+ ReadVIMulAddV_MX, ReadVMask]>;
defm "" : VPseudoTernaryV_VX_AAXA<m, Constraint>,
Sched<[WriteVIMulAddX_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
- ReadVIMulAddX_MX, ReadVMask]>;
+ ReadVIMulAddX_MX, ReadVMask]>;
}
}
@@ -2921,10 +2921,10 @@ multiclass VPseudoVWMAC_VV_VX {
defm "" : VPseudoTernaryW_VV_LMUL<m>,
Sched<[WriteVIWMulAddV_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
- ReadVIWMulAddV_MX, ReadVMask]>;
+ ReadVIWMulAddV_MX, ReadVMask]>;
defm "" : VPseudoTernaryW_VX<m>,
Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
- ReadVIWMulAddX_MX, ReadVMask]>;
+ ReadVIWMulAddX_MX, ReadVMask]>;
}
}
@@ -2937,7 +2937,7 @@ multiclass VPseudoVWMAC_VX {
defm "" : VPseudoTernaryW_VX<m>,
Sched<[WriteVIWMulAddX_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
- ReadVIWMulAddX_MX, ReadVMask]>;
+ ReadVIWMulAddX_MX, ReadVMask]>;
}
}
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