[PATCH] D137705: [AMDGPU] Add DAG Combine for right-shift carry add to uaddo

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Seems to be correct https://alive2.llvm.org/ce/z/VN9-vU



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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3205
 
+  // fold (i64 (shr (add a, b), 32)) -> (uaddo a, b).overflow
+  //   iff a/b have >= 32 leading zeroes
----------------
arsenm wrote:
> Should also move to generic code 
This is missing the extends in the input and output 


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3221
+      bool CanCombine = true;
+      for (SDNode *User : LHS->uses()) {
+        if (User == N)
----------------
Looking at uses is unusual and I'm not sure why you're doing it


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Comment at: llvm/test/CodeGen/AMDGPU/add_shr_carry.ll:6
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefix=GFX11 %s
+
+define i64 @basic_zext(i32 %a, i32 %b, i64 %c) {
----------------
Should precommit this test to show the diff 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137705/new/

https://reviews.llvm.org/D137705